Merge changes from topic "nxp-clk/add_usdhc_clock" into integration

* changes:
feat(s32g274a): enable sdhc clock
feat(nxp-clk): add clock modules for uSDHC
feat(nxp-clk): get MC_CGM divider's

Merge changes from topic "nxp-clk/add_usdhc_clock" into integration

* changes:
feat(s32g274a): enable sdhc clock
feat(nxp-clk): add clock modules for uSDHC
feat(nxp-clk): get MC_CGM divider's parent
feat(nxp-clk): get MC_CGM divider's rate
feat(nxp-clk): set MC_CGM divider's rate
feat(nxp-clk): enable MC_CGM dividers
feat(nxp-clk): get parent for the fixed dividers
feat(nxp-clk): set the rate for partition objects
feat(nxp-clk): add clock objects for CGM dividers
feat(nxp-clk): add base address for PERIPH_DFS

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feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: I

feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: Id2786a46c5a1d389ca32a4839c7158949aec3b0a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-clk/add_get_rate" into integration

* changes:
feat(nxp-clk): restore pll output dividers rate
feat(nxp-clk): get pll rate using get_module_rate
feat(nxp-clk): add

Merge changes from topic "nxp-clk/add_get_rate" into integration

* changes:
feat(nxp-clk): restore pll output dividers rate
feat(nxp-clk): get pll rate using get_module_rate
feat(nxp-clk): add get_rate for partition objects
feat(nxp-clk): add get_rate for clock muxes
feat(nxp-clk): add get_rate for s32cc_pll_out_div
feat(nxp-clk): add get_rate for s32cc_fixed_div
feat(nxp-clk): add get_rate for s32cc_dfs_div
feat(nxp-clk): add get_rate for s32cc_dfs
feat(nxp-clk): add get_rate for s32cc_pll
feat(nxp-clk): add get_rate for s32cc_clk
feat(nxp-clk): add a basic get_rate implementation

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feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add mor

feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add more objects to this list.

Change-Id: I8c1bbbfa6b116fdcf5a1f1353bdb52b474bac831
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add object

Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add objects needed for DDR clock
feat(nxp-clk): setup the DDR PLL
feat(nxp-clk): add MC_ME utilities
feat(nxp-clk): add partition reset utilities
feat(nxp-clk): add partitions objects

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feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition

feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.

Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi

feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add partitions objects

The S32CC-based SoCs are organized in partitions. These are
software-resettable domains in which configuration participates in
MC_CGM, MC_ME, and RDC modules. A

feat(nxp-clk): add partitions objects

The S32CC-based SoCs are organized in partitions. These are
software-resettable domains in which configuration participates in
MC_CGM, MC_ME, and RDC modules. A partition is an island that may
contain multiple blocks, each of which corresponds to a peripheral or a
core and can, in most cases, be reset individually. This reset structure
results in better device availability. If a fault is detected in a
software reset domain, that domain can be reset separately without
impacting the operation of the rest of the chip.

Change-Id: Ie60dbe151309209e377aa71356dbbd6a4f376a8c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-drivers/add-linflex-clk" into integration

* changes:
feat(nxp-clk): enable UART clock
feat(nxp-clk): add PERIPH PLL enablement

feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or

feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.

Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 in

Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 instance
feat(nxp-clk): add DFS module enablement
feat(nxp-clk): add clock objects for ARM DFS
refactor(nxp-clk): organize early clocks in groups

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feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procop

feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for ARM DFS

The DFS modules are connected to the PLL VCO and provide a clock
downstream through a set of output dividers, the frequency of which can
be adjusted prog

feat(nxp-clk): add clock objects for ARM DFS

The DFS modules are connected to the PLL VCO and provide a clock
downstream through a set of output dividers, the frequency of which can
be adjusted programmatically.

Change-Id: Ie945d10fd39e6e40e6c051ccde8486dcfb5bd53f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "clk_fixed_divider" into integration

* changes:
feat(nxp-clk): set rate for clock fixed divider
feat(nxp-clk): add A53 clock objects
feat(nxp-clk): set rate for PLL di

Merge changes from topic "clk_fixed_divider" into integration

* changes:
feat(nxp-clk): set rate for clock fixed divider
feat(nxp-clk): add A53 clock objects
feat(nxp-clk): set rate for PLL divider objects
feat(nxp-clk): set rate for PLL objects

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feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c39640

feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for PLL objects

Add implementation for ARM PLL rate set mechanism.

Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopci

feat(nxp-clk): set rate for PLL objects

Add implementation for ARM PLL rate set mechanism.

Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "add_s32cc_pll" into integration

* changes:
feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes
feat(nxp-clk): add MC_CGM clock objects
feat(nxp-clk): add set_paren

Merge changes from topic "add_s32cc_pll" into integration

* changes:
feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes
feat(nxp-clk): add MC_CGM clock objects
feat(nxp-clk): add set_parent callback
feat(nxp-clk): add clock objects for ARM PLL
feat(nxp-clk): add FXOSC clock enablement

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feat(nxp-clk): add MC_CGM clock objects

The MC_CGM1 clock objects will participate in A53 clocking.

Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi

feat(nxp-clk): add MC_CGM clock objects

The MC_CGM1 clock objects will participate in A53 clocking.

Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add set_parent callback

On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs

feat(nxp-clk): add set_parent callback

On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs and MC_CGM muxes.

Change-Id: I7228d379500ea790459b858da8fc0bdcbed4fd62
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for ARM PLL

Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.

Change-Id: I2585ed38178ca1d5c5485adb

feat(nxp-clk): add clock objects for ARM PLL

Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.

Change-Id: I2585ed38178ca1d5c5485adb38af1b3b8d94f1f6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "add_s32cc_fxosc_clk" into integration

* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillat

Merge changes from topic "add_s32cc_fxosc_clk" into integration

* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillator clock objects
feat(nxp-clk): add minimal set of S32CC clock ids

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feat(nxp-clk): implement set_rate for oscillators

The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this

feat(nxp-clk): implement set_rate for oscillators

The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this capability.

Change-Id: I82d1545c63b3e15497c1c002ff9ec0d7bf990aa0
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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