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/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgicdv3_helpers.c22 void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) in gicd_set_icfgr() argument
28 mmio_clrsetbits_32(base + GICD_OFFSET(ICFG, id), in gicd_set_icfgr()
37 unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) in gicd_get_igroupr() argument
39 return GICD_GET_BIT(IGROUP, base, id); in gicd_get_igroupr()
42 void gicd_set_igroupr(uintptr_t base, unsigned int id) in gicd_set_igroupr() argument
44 GICD_SET_BIT(IGROUP, base, id); in gicd_set_igroupr()
47 void gicd_clr_igroupr(uintptr_t base, unsigned int id) in gicd_clr_igroupr() argument
49 GICD_CLR_BIT(IGROUP, base, id); in gicd_clr_igroupr()
56 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id) in gicd_get_igrpmodr() argument
58 return GICD_GET_BIT(IGRPMOD, base, id); in gicd_get_igrpmodr()
[all …]
H A Dgicv3_private.h70 #define GICD_READ(REG, base, id) \ argument
71 mmio_read_32((base) + GICD_OFFSET(REG, (id)))
73 #define GICD_READ_64(REG, base, id) \ argument
74 mmio_read_64((base) + GICD_OFFSET_64(REG, (id)))
76 #define GICD_WRITE_8(REG, base, id, val) \ argument
77 mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val))
79 #define GICD_WRITE(REG, base, id, val) \ argument
80 mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val))
82 #define GICD_WRITE_64(REG, base, id, val) \ argument
83 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
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H A Dgic600ae_fmu_helpers.c19 #define GIC_FMU_WRITE_32(base, reg, val) \ argument
25 mmio_write_32(base + GICFMU_KEY, 0xBE); \
27 mmio_write_32((base) + (reg), (val)); \
31 #define GIC_FMU_WRITE_64(base, reg, n, val) \ argument
37 mmio_write_32(base + GICFMU_KEY, 0xBE); \
42 mmio_write_32((base) + reg##_LO + (n * 64), (val)); \
43 mmio_write_32((base) + reg##_HI + (n * 64), (val)); \
47 static void wait_until_fmu_is_idle(uintptr_t base) in wait_until_fmu_is_idle() argument
54 status = (gic_fmu_read_status(base) & BIT(0)); in wait_until_fmu_is_idle()
66 #define GIC_FMU_WRITE_ON_IDLE_32(base, reg, val) \ argument
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H A Dgicrv3_helpers.c24 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) in gicr_read_ipriorityr() argument
26 return GICR_READ(IPRIORITY, base, id); in gicr_read_ipriorityr()
29 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) in gicr_write_ipriorityr() argument
31 GICR_WRITE(IPRIORITY, base, id, val); in gicr_write_ipriorityr()
38 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) in gicr_set_ipriorityr() argument
40 GICR_WRITE_8(IPRIORITY, base, id, (uint8_t)(pri & GIC_PRI_MASK)); in gicr_set_ipriorityr()
47 unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id) in gicr_get_igroupr() argument
49 return GICR_GET_BIT(IGROUP, base, id); in gicr_get_igroupr()
52 void gicr_set_igroupr(uintptr_t base, unsigned int id) in gicr_set_igroupr() argument
54 GICR_SET_BIT(IGROUP, base, id); in gicr_set_igroupr()
[all …]
/rk3399_ARM-atf/drivers/arm/gic/common/
H A Dgic_common_private.h18 static inline unsigned int gicd_read_ctlr(uintptr_t base) in gicd_read_ctlr() argument
20 return mmio_read_32(base + GICD_CTLR); in gicd_read_ctlr()
23 static inline unsigned int gicd_read_typer(uintptr_t base) in gicd_read_typer() argument
25 return mmio_read_32(base + GICD_TYPER); in gicd_read_typer()
28 static inline unsigned int gicd_read_iidr(uintptr_t base) in gicd_read_iidr() argument
30 return mmio_read_32(base + GICD_IIDR); in gicd_read_iidr()
33 static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) in gicd_write_ctlr() argument
35 mmio_write_32(base + GICD_CTLR, val); in gicd_write_ctlr()
43 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id);
44 unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id);
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H A Dgic_common.c23 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) in gicd_read_igroupr() argument
27 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); in gicd_read_igroupr()
34 unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) in gicd_read_isenabler() argument
38 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); in gicd_read_isenabler()
45 unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) in gicd_read_icenabler() argument
49 return mmio_read_32(base + GICD_ICENABLER + (n << 2)); in gicd_read_icenabler()
56 unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) in gicd_read_ispendr() argument
60 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); in gicd_read_ispendr()
67 unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) in gicd_read_icpendr() argument
71 return mmio_read_32(base + GICD_ICPENDR + (n << 2)); in gicd_read_icpendr()
[all …]
/rk3399_ARM-atf/drivers/arm/gic/v2/
H A Dgicv2_private.h25 unsigned int gicv2_get_cpuif_id(uintptr_t base);
30 static inline unsigned int gicd_read_pidr2(uintptr_t base) in gicd_read_pidr2() argument
32 return mmio_read_32(base + GICD_PIDR2_GICV2); in gicd_read_pidr2()
38 static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id) in gicd_get_itargetsr() argument
40 return mmio_read_8(base + GICD_ITARGETSR + id); in gicd_get_itargetsr()
43 static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id, in gicd_set_itargetsr() argument
48 mmio_write_8(base + GICD_ITARGETSR + id, val); in gicd_set_itargetsr()
51 static inline void gicd_write_sgir(uintptr_t base, unsigned int val) in gicd_write_sgir() argument
53 mmio_write_32(base + GICD_SGIR, val); in gicd_write_sgir()
60 static inline unsigned int gicc_read_ctlr(uintptr_t base) in gicc_read_ctlr() argument
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H A Dgicdv2_helpers.c22 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) in gicd_read_igroupr() argument
26 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); in gicd_read_igroupr()
33 unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) in gicd_read_isenabler() argument
37 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); in gicd_read_isenabler()
44 unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) in gicd_read_icenabler() argument
48 return mmio_read_32(base + GICD_ICENABLER + (n << 2)); in gicd_read_icenabler()
55 unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) in gicd_read_ispendr() argument
59 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); in gicd_read_ispendr()
66 unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) in gicd_read_icpendr() argument
70 return mmio_read_32(base + GICD_ICPENDR + (n << 2)); in gicd_read_icpendr()
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/rk3399_ARM-atf/plat/hisilicon/hikey960/drivers/pwrc/
H A Dhisi_pwrc.h16 #define SOC_CRGPERIPH_A53_PDCEN_ADDR(base) ((base) + (0x260)) argument
17 #define SOC_CRGPERIPH_MAIA_PDCEN_ADDR(base) ((base) + (0x300)) argument
19 #define SOC_PCTRL_RESOURCE0_LOCK_ADDR(base) ((base) + (0x400)) argument
20 #define SOC_PCTRL_RESOURCE0_UNLOCK_ADDR(base) ((base) + (0x404)) argument
21 #define SOC_PCTRL_RESOURCE0_LOCK_ST_ADDR(base) ((base) + (0x408)) argument
22 #define SOC_PCTRL_RESOURCE1_LOCK_ADDR(base) ((base) + (0x40C)) argument
23 #define SOC_PCTRL_RESOURCE1_UNLOCK_ADDR(base) ((base) + (0x410)) argument
24 #define SOC_PCTRL_RESOURCE1_LOCK_ST_ADDR(base) ((base) + (0x414)) argument
25 #define SOC_PCTRL_RESOURCE2_LOCK_ADDR(base) ((base) + (0x418)) argument
27 #define SOC_SCTRL_SCBAKDATA3_ADDR(base) ((base) + (0x418)) argument
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/uart/
H A Duart.c21 unsigned long base; in mt_uart_restore() local
28 base = uart->base; in mt_uart_restore()
30 mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); in mt_uart_restore()
31 mmio_write_32(UART_EFR(base), uart->registers.efr); in mt_uart_restore()
32 mmio_write_32(UART_LCR(base), uart->registers.lcr); in mt_uart_restore()
33 mmio_write_32(UART_FCR(base), uart->registers.fcr); in mt_uart_restore()
36 mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed); in mt_uart_restore()
37 mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l); in mt_uart_restore()
38 mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m); in mt_uart_restore()
39 mmio_write_32(UART_LCR(base), in mt_uart_restore()
[all …]
/rk3399_ARM-atf/drivers/arm/sp805/
H A Dsp805.c14 static inline void sp805_write_wdog_load(uintptr_t base, uint32_t value) in sp805_write_wdog_load() argument
16 mmio_write_32(base + SP805_WDOG_LOAD_OFF, value); in sp805_write_wdog_load()
19 static inline void sp805_write_wdog_ctrl(uintptr_t base, uint32_t value) in sp805_write_wdog_ctrl() argument
21 mmio_write_32(base + SP805_WDOG_CTR_OFF, value); in sp805_write_wdog_ctrl()
24 static inline void sp805_write_wdog_lock(uintptr_t base, uint32_t value) in sp805_write_wdog_lock() argument
26 mmio_write_32(base + SP805_WDOG_LOCK_OFF, value); in sp805_write_wdog_lock()
32 void sp805_start(uintptr_t base, unsigned int ticks) in sp805_start() argument
34 sp805_write_wdog_load(base, ticks); in sp805_start()
35 sp805_write_wdog_ctrl(base, SP805_CTR_RESEN | SP805_CTR_INTEN); in sp805_start()
37 sp805_write_wdog_lock(base, 0U); in sp805_start()
[all …]
/rk3399_ARM-atf/drivers/arm/tzc/
H A Dtzc400.c34 uintptr_t base; member
42 static inline unsigned int _tzc400_read_build_config(uintptr_t base) in _tzc400_read_build_config() argument
44 return mmio_read_32(base + BUILD_CONFIG_OFF); in _tzc400_read_build_config()
47 static inline unsigned int _tzc400_read_gate_keeper(uintptr_t base) in _tzc400_read_gate_keeper() argument
49 return mmio_read_32(base + GATE_KEEPER_OFF); in _tzc400_read_gate_keeper()
52 static inline void _tzc400_write_gate_keeper(uintptr_t base, unsigned int val) in _tzc400_write_gate_keeper() argument
54 mmio_write_32(base + GATE_KEEPER_OFF, val); in _tzc400_write_gate_keeper()
75 static void _tzc400_clear_it(uintptr_t base, uint32_t filter) in _tzc400_clear_it() argument
77 mmio_write_32(base + INT_CLEAR, BIT_32(filter)); in _tzc400_clear_it()
80 static uint32_t _tzc400_get_int_by_filter(uintptr_t base, uint32_t filter) in _tzc400_get_int_by_filter() argument
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H A Dtzc380.c15 uintptr_t base; member
22 static unsigned int tzc380_read_build_config(uintptr_t base) in tzc380_read_build_config() argument
24 return mmio_read_32(base + TZC380_CONFIGURATION_OFF); in tzc380_read_build_config()
27 static void tzc380_write_action(uintptr_t base, unsigned int action) in tzc380_write_action() argument
29 mmio_write_32(base + ACTION_OFF, action); in tzc380_write_action()
32 static void tzc380_write_region_base_low(uintptr_t base, unsigned int region, in tzc380_write_region_base_low() argument
35 mmio_write_32(base + REGION_SETUP_LOW_OFF(region), val); in tzc380_write_region_base_low()
38 static void tzc380_write_region_base_high(uintptr_t base, unsigned int region, in tzc380_write_region_base_high() argument
41 mmio_write_32(base + REGION_SETUP_HIGH_OFF(region), val); in tzc380_write_region_base_high()
44 static void tzc380_write_region_attributes(uintptr_t base, unsigned int region, in tzc380_write_region_attributes() argument
[all …]
H A Dtzc_common_private.h17 uintptr_t base, \
20 mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \
26 uintptr_t base, \
30 mmio_write_32(base + \
36 mmio_write_32(base + \
46 uintptr_t base, \
50 mmio_write_32(base + \
56 mmio_write_32(base + \
66 uintptr_t base, \
70 mmio_write_32(base + \
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/rk3399_ARM-atf/drivers/brcm/
H A Docotp.c59 uint32_t base; member
64 .base = OTPC_MODE_REG,
69 uint32_t base; member
77 static inline void set_command(uint32_t base, uint32_t command) in set_command() argument
79 mmio_write_32(base + OTPC_COMMAND_OFFSET, command & OTPC_CMD_MASK); in set_command()
82 static inline void set_cpu_address(uint32_t base, uint32_t addr) in set_cpu_address() argument
84 mmio_write_32(base + OTPC_CPUADDR_REG_OFFSET, addr & OTPC_ADDR_MASK); in set_cpu_address()
87 static inline void set_start_bit(uint32_t base) in set_start_bit() argument
89 mmio_write_32(base + OTPC_CMD_START_OFFSET, 1 << OTPC_CMD_START_START); in set_start_bit()
92 static inline void reset_start_bit(uint32_t base) in reset_start_bit() argument
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/rk3399_ARM-atf/plat/imx/common/sci/
H A Dimx8_mu.c11 void MU_Resume(uint32_t base) in MU_Resume() argument
15 reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_Resume()
19 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_Resume()
23 MU_EnableRxFullInt(base, i); in MU_Resume()
26 void MU_EnableRxFullInt(uint32_t base, uint32_t index) in MU_EnableRxFullInt() argument
28 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableRxFullInt()
32 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableRxFullInt()
35 void MU_EnableGeneralInt(uint32_t base, uint32_t index) in MU_EnableGeneralInt() argument
37 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableGeneralInt()
41 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableGeneralInt()
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H A Dipc.c36 uint32_t base = id; in sc_ipc_open() local
40 if ((ipc == NULL) || (base == 0)) in sc_ipc_open()
46 MU_Init(base); in sc_ipc_open()
50 MU_EnableRxFullInt(base, i); in sc_ipc_open()
61 uint32_t base = ipc; in sc_ipc_close() local
63 if (base != 0) in sc_ipc_close()
64 MU_Init(base); in sc_ipc_close()
69 uint32_t base = ipc; in sc_ipc_read() local
74 if ((base == 0) || (msg == NULL)) in sc_ipc_read()
78 MU_ReceiveMsg(base, 0, (uint32_t *) msg); in sc_ipc_read()
[all …]
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_console_setup.c51 uintptr_t base, end; in uniphier_console_get_base() local
55 base = uniphier_uart_base[soc]; in uniphier_console_get_base()
56 end = base + UNIPHIER_UART_OFFSET * UNIPHIER_UART_NR_PORTS; in uniphier_console_get_base()
58 while (base < end) { in uniphier_console_get_base()
59 div = mmio_read_32(base + UNIPHIER_UART_DLR); in uniphier_console_get_base()
61 return base; in uniphier_console_get_base()
62 base += UNIPHIER_UART_OFFSET; in uniphier_console_get_base()
68 static void uniphier_console_init(uintptr_t base) in uniphier_console_init() argument
70 mmio_write_32(base + UNIPHIER_UART_FCR, UNIPHIER_UART_FCR_ENABLE_FIFO); in uniphier_console_init()
71 mmio_write_32(base + UNIPHIER_UART_LCR_MCR, in uniphier_console_init()
[all …]
/rk3399_ARM-atf/drivers/marvell/mochi/
H A Dcp110_setup.c153 static void cp110_errata_wa_init(uintptr_t base) in cp110_errata_wa_init() argument
167 data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM)); in cp110_errata_wa_init()
169 mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data); in cp110_errata_wa_init()
172 static void cp110_pcie_clk_cfg(uintptr_t base) in cp110_pcie_clk_cfg() argument
180 reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG); in cp110_pcie_clk_cfg()
185 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 || in cp110_pcie_clk_cfg()
186 cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) { in cp110_pcie_clk_cfg()
191 reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL); in cp110_pcie_clk_cfg()
198 mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg); in cp110_pcie_clk_cfg()
202 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) { in cp110_pcie_clk_cfg()
[all …]
/rk3399_ARM-atf/plat/rpi/common/
H A Drpi_pci_svc.c46 uint64_t base; in pci_segment_lib_get_base() local
56 base = pcie_rc_bases[seg]; in pci_segment_lib_get_base()
74 uint32_t status = mmio_read_32(base + PCIE_MISC_PCIE_STATUS); in pci_segment_lib_get_base()
85 mmio_write_32(base + PCIE_EXT_CFG_INDEX, address << PCIE_EXT_CFG_BDF_SHIFT); in pci_segment_lib_get_base()
86 base += PCIE_EXT_CFG_DATA; in pci_segment_lib_get_base()
89 return base + (offset & PCI_OFFSET_MASK); in pci_segment_lib_get_base()
116 uint64_t base; in pci_read_config() local
119 base = pci_segment_lib_get_base(addr, off); in pci_read_config()
121 if (base == INVALID_PCI_ADDR) { in pci_read_config()
122 *val = base; in pci_read_config()
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/rk3399_ARM-atf/drivers/st/crypto/
H A Dstm32_saes.c164 if ((info.base == 0U) || (info.clock < 0) || (info.reset < 0)) { in stm32_saes_parse_fdt()
168 pdata->base = (uintptr_t)info.base; in stm32_saes_parse_fdt()
190 static int wait_computation_completed(uintptr_t base) in wait_computation_completed() argument
194 while ((mmio_read_32(base + _SAES_SR) & _SAES_SR_CCF) != _SAES_SR_CCF) { in wait_computation_completed()
204 static void clear_computation_completed(uintptr_t base) in clear_computation_completed() argument
206 mmio_setbits_32(base + _SAES_ICR, _SAES_I_CC); in clear_computation_completed()
214 if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) != _SAES_SR_BUSY) { in saes_start()
215 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); in saes_start()
217 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); in saes_start()
221 while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) { in saes_start()
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H A Dstm32_rng.c69 uintptr_t base; member
80 mmio_clrbits_32(stm32_rng.base + RNG_SR, RNG_SR_SEIS); in seed_error_recovery()
86 (void)mmio_read_32(stm32_rng.base + RNG_DR); in seed_error_recovery()
92 if ((mmio_read_32(stm32_rng.base + RNG_SR) & RNG_SR_SEIS) != 0U) { in seed_error_recovery()
126 mmio_write_32(stm32_rng.base + RNG_CR, RNG_CR_RNGEN | RNG_CR_CED); in stm32_rng_enable()
133 mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_NIST_CONFIG_MASK, in stm32_rng_enable()
136 mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CLKDIV, in stm32_rng_enable()
139 mmio_write_32(stm32_rng.base + RNG_HTCR, RNG_HTCFG_CONFIG); in stm32_rng_enable()
141 mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CONDRST, RNG_CR_RNGEN); in stm32_rng_enable()
144 sr = mmio_read_32(stm32_rng.base + RNG_SR); in stm32_rng_enable()
[all …]
/rk3399_ARM-atf/plat/marvell/armada/a8k/common/mss/
H A Dmss_defs.h11 #define MSS_DMA_SRCBR(base) (base + 0xC0) argument
12 #define MSS_DMA_DSTBR(base) (base + 0xC4) argument
13 #define MSS_DMA_CTRLR(base) (base + 0xC8) argument
14 #define MSS_M3_RSTCR(base) (base + 0xFC) argument
/rk3399_ARM-atf/plat/mediatek/drivers/mminfra/mt8196/
H A Dmminfra.c23 .base = MMINFRA_HW_VOTER_BASE,
31 .base = SPM_BASE,
49 static int spm_semaphore_get(uint32_t base, uint32_t set_val) in spm_semaphore_get() argument
54 val = mmio_read_32(base); in spm_semaphore_get()
57 base, val, set_val); in spm_semaphore_get()
62 mmio_write_32(base, set_val); in spm_semaphore_get()
64 if ((mmio_read_32(base) & set_val) == set_val) in spm_semaphore_get()
69 mminfra_err("timeout! base:0x%x, set_val:0x%x\n", base, set_val); in spm_semaphore_get()
73 static int spm_semaphore_release(uint32_t base, uint32_t set_val) in spm_semaphore_release() argument
78 val = mmio_read_32(base); in spm_semaphore_release()
[all …]
/rk3399_ARM-atf/include/drivers/arm/
H A Dgic600ae_fmu.h130 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n);
131 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n);
132 uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n);
133 uint64_t gic_fmu_read_errgsr(uintptr_t base);
134 uint32_t gic_fmu_read_pingctlr(uintptr_t base);
135 uint32_t gic_fmu_read_pingnow(uintptr_t base);
136 uint64_t gic_fmu_read_pingmask(uintptr_t base);
137 uint32_t gic_fmu_read_status(uintptr_t base);
138 uint32_t gic_fmu_read_erridr(uintptr_t base);
139 void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val);
[all …]

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