153 static void cp110_errata_wa_init(uintptr_t base)  in cp110_errata_wa_init()  argument
167 	data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM));  in cp110_errata_wa_init()
169 	mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data);  in cp110_errata_wa_init()
172 static void cp110_pcie_clk_cfg(uintptr_t base)  in cp110_pcie_clk_cfg()  argument
180 	reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG);  in cp110_pcie_clk_cfg()
185 	if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 ||  in cp110_pcie_clk_cfg()
186 	    cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) {  in cp110_pcie_clk_cfg()
191 		reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL);  in cp110_pcie_clk_cfg()
198 		mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg);  in cp110_pcie_clk_cfg()
202 	if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) {  in cp110_pcie_clk_cfg()
209 			reg = mmio_read_32(base + MVEBU_CP_MSS_DPSHSR_REG);  in cp110_pcie_clk_cfg()
211 			mmio_write_32(base + MVEBU_CP_MSS_DPSHSR_REG, reg);  in cp110_pcie_clk_cfg()
217 static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id)  in cp110_stream_id_init()  argument
230 			mmio_write_32(base + stream_id_reg[i],  in cp110_stream_id_init()
233 			mmio_write_32(base + stream_id_reg[i], stream_id);  in cp110_stream_id_init()
245 static void cp110_axi_attr_init(uintptr_t base)  in cp110_axi_attr_init()  argument
266 			data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index));  in cp110_axi_attr_init()
284 			mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data);  in cp110_axi_attr_init()
291 	data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG);  in cp110_axi_attr_init()
302 	mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data);  in cp110_axi_attr_init()
306 		mmio_write_32(base + MVEBU_AXI_PROT_REG(index),  in cp110_axi_attr_init()
310 void cp110_amb_init(uintptr_t base)  in cp110_amb_init()  argument
315 	reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0));  in cp110_amb_init()
320 	mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg);  in cp110_amb_init()
323 static void cp110_rtc_init(uintptr_t base)  in cp110_rtc_init()  argument
326 	mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,  in cp110_rtc_init()
330 	mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,  in cp110_rtc_init()
335 	mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG,  in cp110_rtc_init()
343 	if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) &  in cp110_rtc_init()
346 		mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0);  in cp110_rtc_init()
350 		mmio_write_32(base + MVEBU_RTC_STATUS_REG,  in cp110_rtc_init()
356 		mmio_write_32(base + MVEBU_RTC_IRQ_1_CONFIG_REG, 0);  in cp110_rtc_init()
357 		mmio_write_32(base + MVEBU_RTC_IRQ_2_CONFIG_REG, 0);  in cp110_rtc_init()
358 		mmio_write_32(base + MVEBU_RTC_ALARM_1_REG, 0);  in cp110_rtc_init()
359 		mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0);  in cp110_rtc_init()
362 		mmio_write_32(base + MVEBU_RTC_CCR_REG,  in cp110_rtc_init()
366 		mmio_write_32(base + MVEBU_RTC_STATUS_REG,  in cp110_rtc_init()
373 static void cp110_amb_adec_init(uintptr_t base)  in cp110_amb_adec_init()  argument
376 	mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG,  in cp110_amb_adec_init()
380 	init_amb_adec(base);  in cp110_amb_adec_init()