Lines Matching refs:base
69 uintptr_t base; member
80 mmio_clrbits_32(stm32_rng.base + RNG_SR, RNG_SR_SEIS); in seed_error_recovery()
86 (void)mmio_read_32(stm32_rng.base + RNG_DR); in seed_error_recovery()
92 if ((mmio_read_32(stm32_rng.base + RNG_SR) & RNG_SR_SEIS) != 0U) { in seed_error_recovery()
126 mmio_write_32(stm32_rng.base + RNG_CR, RNG_CR_RNGEN | RNG_CR_CED); in stm32_rng_enable()
133 mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_NIST_CONFIG_MASK, in stm32_rng_enable()
136 mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CLKDIV, in stm32_rng_enable()
139 mmio_write_32(stm32_rng.base + RNG_HTCR, RNG_HTCFG_CONFIG); in stm32_rng_enable()
141 mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CONDRST, RNG_CR_RNGEN); in stm32_rng_enable()
144 sr = mmio_read_32(stm32_rng.base + RNG_SR); in stm32_rng_enable()
157 sr = mmio_read_32(stm32_rng.base + RNG_SR); in stm32_rng_enable()
168 uint32_t status = mmio_read_32(stm32_rng.base + RNG_SR); in check_data_validity()
184 status = mmio_read_32(stm32_rng.base + RNG_SR); in check_data_validity()
205 if (stm32_rng.base == 0U) { in stm32_rng_read()
217 if ((mmio_read_32(stm32_rng.base + RNG_SR) & RNG_SR_DRDY) == 0U) { in stm32_rng_read()
221 data32 = mmio_read_32(stm32_rng.base + RNG_DR); in stm32_rng_read()
229 data32 = mmio_read_32(stm32_rng.base + RNG_DR); in stm32_rng_read()
258 if ((stm32_rng.base == 0U) || (stm32_rng.clock == 0U)) { in stm32_rng_select()
260 stm32_rng.base = rng_base; in stm32_rng_select()
276 if (stm32_rng.base != 0U) { in stm32_rng_init()
282 rng.base = stm32_rng.base; in stm32_rng_init()
295 VERBOSE("Setting up rng@%x, status: %x\n", dt_rng.base, dt_rng.status); in stm32_rng_init()
302 if ((dt_rng.status == DT_DISABLED) || (dt_rng.base == 0U)) { in stm32_rng_init()
307 stm32_rng.base = dt_rng.base; in stm32_rng_init()
316 if (stm32_rng.base == rng.base) { in stm32_rng_init()
338 ERROR("Failed to enable rng@%x\n", dt_rng.base); in stm32_rng_init()
348 if ((rng.clock != 0U) && (rng.base != 0U)) { in stm32_rng_init()