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Searched refs:SOCFPGA_SYSMGR (Results 1 – 25 of 31) sorted by relevance

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/rk3399_ARM-atf/plat/intel/soc/common/drivers/ccu/
H A Dncore_ccu.c627 mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_ID_AX_REG_0_DMA0), DMA0); in setup_smmu_stream_id()
628 mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_ID_AX_REG_0_DMA1), DMA1); in setup_smmu_stream_id()
629 mmio_write_32(SOCFPGA_SYSMGR(SDM_TBU_STREAM_ID_AX_REG_1_SDM), SDM); in setup_smmu_stream_id()
631 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_USB2), USB0); in setup_smmu_stream_id()
633 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_USB3), USB1); in setup_smmu_stream_id()
634 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_SDMMC), SDMMC); in setup_smmu_stream_id()
635 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_NAND), NAND); in setup_smmu_stream_id()
637 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_ETR), CORE_SIGHT_DEBUG); in setup_smmu_stream_id()
638 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN0), TSN0); in setup_smmu_stream_id()
639 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN1), TSN1); in setup_smmu_stream_id()
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_emac.c22 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_0), in socfpga_emac_init()
24 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_1), in socfpga_emac_init()
26 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_2), in socfpga_emac_init()
29 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), in socfpga_emac_init()
H A Dsocfpga_reset_manager.c491 mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL), in socfpga_bridges_enable()
579 mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL), in socfpga_bridges_enable()
585 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), in socfpga_bridges_enable()
592 ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), in socfpga_bridges_enable()
684 mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL), in socfpga_bridges_enable()
934 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL), in socfpga_bridges_disable()
974 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL), in socfpga_bridges_disable()
981 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), in socfpga_bridges_disable()
984 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); in socfpga_bridges_disable()
986 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), in socfpga_bridges_disable()
[all …]
H A Dsocfpga_system_manager.c20 jtag_id = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_4))); in intel_hps_get_jtag_id()
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_ddr.c125 uint32_t sys_reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0)); in is_ddr_init_hang()
139 mmio_setbits_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0), in ddr_init_inprogress()
142 mmio_clrbits_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0), in ddr_init_inprogress()
178 uint32_t sys_reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_3)); in hps_ocram_dbe_status()
188 uint32_t sys_reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_3)); in ddr_ecc_dbe_status()
321 enum reset_type reset_t = get_reset_type(mmio_read_32(SOCFPGA_SYSMGR( in agilex5_ddr_init()
345 mmio_setbits_32(SOCFPGA_SYSMGR(MPFE_CONFIG), BIT(8)); in agilex5_ddr_init()
348 mmio_setbits_32(SOCFPGA_SYSMGR(MPFE_CONFIG), BIT(2)); in agilex5_ddr_init()
H A Dagilex5_pinmux.c207 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), fpgaintf_en_val); in config_fpgaintf_mod()
220 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), fpgaintf_en_val); in config_fpgaintf_mod()
H A Dagilex5_clock_manager.c332 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), hoff_ptr->hps_osc_clk_hz); in config_clkmgr_handoff()
333 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), hoff_ptr->fpga_clk_hz); in config_clkmgr_handoff()
373 ref_clk = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)); in get_ref_clk()
381 ref_clk = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2)); in get_ref_clk()
426 clock = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)); in get_clk_freq()
434 clock = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2)); in get_clk_freq()
/rk3399_ARM-atf/plat/intel/soc/common/drivers/combophy/
H A Dcombophy.c52 mmio_setbits_32(SOCFPGA_SYSMGR(DFI_INTF), active_dfi_intf); in dfi_select()
55 reg = mmio_read_32(SOCFPGA_SYSMGR(DFI_INTF)); in dfi_select()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_pinmux.c202 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), val); in config_fpgaintf_mod()
211 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), val); in config_fpgaintf_mod()
H A Dagilex_mmc.c15 mmio_write_32(SOCFPGA_SYSMGR(SDMMC), in agx_mmc_init()
H A Dagilex_clock_manager.c272 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), in config_clkmgr_handoff()
274 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), in config_clkmgr_handoff()
286 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); in get_ref_clk()
293 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); in get_ref_clk()
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c164 reg_val = mmio_read_32(SOCFPGA_SYSMGR(USB3_MISC_CTRL_REG0)); in bl2_el3_early_platform_setup()
166 mmio_write_32(SOCFPGA_SYSMGR(USB3_MISC_CTRL_REG0), reg_val); in bl2_el3_early_platform_setup()
167 VERBOSE("USB3_MISC_CTRL_REG0 = 0x%X\n", mmio_read_32(SOCFPGA_SYSMGR(USB3_MISC_CTRL_REG0))); in bl2_el3_early_platform_setup()
H A Dbl31_plat_setup.c341 value = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_WARM_9)); in bl31_plat_reset_secondary_cpu()
342 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_WARM_9), value | mask); in bl31_plat_reset_secondary_cpu()
344 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_WARM_9), value & ~mask); in bl31_plat_reset_secondary_cpu()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_mmc.c15 mmio_write_32(SOCFPGA_SYSMGR(SDMMC), in s10_mmc_init()
H A Ds10_clock_manager.c193 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), in config_clkmgr_handoff()
195 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), in config_clkmgr_handoff()
208 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); in get_ref_clk()
215 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); in get_ref_clk()
/rk3399_ARM-atf/plat/intel/soc/common/sip/
H A Dsocfpga_sip_ecc.c38 dbe_int_status = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)); in cold_reset_for_ecc_dbe()
/rk3399_ARM-atf/plat/intel/soc/n5x/soc/
H A Dn5x_clock_manager.c32 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); in clk_get_pll_output_hz()
41 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); in clk_get_pll_output_hz()
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_system_manager.h33 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ macro
/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Dsocfpga_plat_def.h127 #define L2_RESET_DONE_REG SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_6)
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dsocfpga_plat_def.h128 #define L2_RESET_DONE_REG SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_6)
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dsocfpga_plat_def.h153 #define L2_RESET_DONE_REG SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_6)
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_psci.c72 psci_boot = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)); in socfpga_pwr_domain_on()
74 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8), psci_boot); in socfpga_pwr_domain_on()
H A Dsocfpga_sip_svc.c377 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN0):
378 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1):
379 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2):
459 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */
460 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */
461 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */
462 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */
463 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */
464 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */
465 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */
[all …]
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dsocfpga_plat_def.h182 #define L2_RESET_DONE_REG SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_3)
/rk3399_ARM-atf/plat/intel/soc/common/drivers/ddr/
H A Dddr.c291 uint32_t reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0)); in is_ddr_init_in_progress()
309 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0), 0x01); in ddr_init()
339 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0), 0x00); in ddr_init()

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