xref: /rk3399_ARM-atf/plat/intel/soc/common/sip/socfpga_sip_ecc.c (revision 816c27fbbaa43ae8d9a59a6e71ef3724190e44f5)
1c703d752SSieu Mun Tang // SPDX-License-Identifier: BSD-3-Clause
2c703d752SSieu Mun Tang /*
3*6197dc98SJit Loon Lim  * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
4c703d752SSieu Mun Tang  */
5c703d752SSieu Mun Tang 
6c703d752SSieu Mun Tang #include <assert.h>
7c703d752SSieu Mun Tang #include <common/debug.h>
8c703d752SSieu Mun Tang #include <common/runtime_svc.h>
9c703d752SSieu Mun Tang #include <lib/mmio.h>
10c703d752SSieu Mun Tang #include <tools_share/uuid.h>
11c703d752SSieu Mun Tang 
12c703d752SSieu Mun Tang #include "socfpga_fcs.h"
13c703d752SSieu Mun Tang #include "socfpga_mailbox.h"
14*6197dc98SJit Loon Lim #include "socfpga_plat_def.h"
15c703d752SSieu Mun Tang #include "socfpga_reset_manager.h"
16c703d752SSieu Mun Tang #include "socfpga_sip_svc.h"
17c703d752SSieu Mun Tang #include "socfpga_system_manager.h"
18c703d752SSieu Mun Tang 
19*6197dc98SJit Loon Lim 
intel_ecc_dbe_notification(uint64_t dbe_value)20c703d752SSieu Mun Tang uint32_t intel_ecc_dbe_notification(uint64_t dbe_value)
21c703d752SSieu Mun Tang {
22c703d752SSieu Mun Tang 	dbe_value &= WARM_RESET_WFI_FLAG;
23c703d752SSieu Mun Tang 
24c703d752SSieu Mun Tang 	/* Trap CPUs in WFI if warm reset flag is set */
25c703d752SSieu Mun Tang 	if (dbe_value > 0) {
26c703d752SSieu Mun Tang 		while (1) {
27c703d752SSieu Mun Tang 			wfi();
28c703d752SSieu Mun Tang 		}
29c703d752SSieu Mun Tang 	}
30c703d752SSieu Mun Tang 
31c703d752SSieu Mun Tang 	return INTEL_SIP_SMC_STATUS_OK;
32c703d752SSieu Mun Tang }
33c703d752SSieu Mun Tang 
cold_reset_for_ecc_dbe(void)34c703d752SSieu Mun Tang bool cold_reset_for_ecc_dbe(void)
35c703d752SSieu Mun Tang {
36c703d752SSieu Mun Tang 	uint32_t dbe_int_status;
37c703d752SSieu Mun Tang 
38c703d752SSieu Mun Tang 	dbe_int_status = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8));
39c703d752SSieu Mun Tang 
40c703d752SSieu Mun Tang 	/* Trigger cold reset only for error in critical memory (DDR/OCRAM) */
41c703d752SSieu Mun Tang 	dbe_int_status &= SYSMGR_ECC_DBE_COLD_RST_MASK;
42c703d752SSieu Mun Tang 
43c703d752SSieu Mun Tang 	if (dbe_int_status > 0) {
44c703d752SSieu Mun Tang 		return true;
45c703d752SSieu Mun Tang 	}
46c703d752SSieu Mun Tang 
47c703d752SSieu Mun Tang 	return false;
48c703d752SSieu Mun Tang }
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