| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.h | 14 PMIC_WRAP_PHASE_ALLINONE = 0U, enumerator
|
| H A D | mt_spm_pmic_wrap.c | 52 .set[PMIC_WRAP_PHASE_ALLINONE] = {
72 .set[PMIC_WRAP_PHASE_ALLINONE] = {
|
| H A D | mt_spm.c | 105 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); in spm_boot_init()
|
| H A D | mt_spm_vcorefs.c | 373 mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val); in spm_vcorefs_pwarp_cmd()
|
| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_plat_spm_setting.h | 17 PMIC_WRAP_PHASE_ALLINONE, enumerator
|
| H A D | mt_plat_spm_setting.c | 231 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); in plat_spm_pmic_wrap_init()
|
| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/ |
| H A D | mt_spm_pmic_wrap.h | 15 PMIC_WRAP_PHASE_ALLINONE = 0, enumerator
|
| H A D | mt_spm.c | 159 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); in spm_boot_init()
|
| H A D | mt_spm_pmic_wrap.c | 60 .set[PMIC_WRAP_PHASE_ALLINONE] = {
|
| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.h | 14 PMIC_WRAP_PHASE_ALLINONE, enumerator
|
| H A D | mt_spm.c | 100 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); in spm_boot_init()
|
| H A D | mt_spm_pmic_wrap.c | 55 .set[PMIC_WRAP_PHASE_ALLINONE] = {
|
| H A D | mt_spm_vcorefs.c | 278 mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val); in spm_vcorefs_pwarp_cmd()
|
| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.h | 14 PMIC_WRAP_PHASE_ALLINONE, enumerator
|
| H A D | mt_spm.c | 94 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); in spm_boot_init()
|
| H A D | mt_spm_pmic_wrap.c | 55 .set[PMIC_WRAP_PHASE_ALLINONE] = {
|
| H A D | mt_spm_vcorefs.c | 362 mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val); in spm_vcorefs_pwarp_cmd()
|
| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_plat_spm_setting.h | 16 PMIC_WRAP_PHASE_ALLINONE, enumerator
|
| H A D | mt_plat_spm_setting.c | 89 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); in plat_spm_pmic_wrap_init()
|
| H A D | mt_vcore_dvfsrc_plat.c | 115 mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val); in spm_vcorefs_pwarp_cmd()
|
| H A D | mt_spm_vcorefs.c | 562 mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, CMD_17, pmic_val); in spm_dvfsfw_init()
|
| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/ |
| H A D | spm_pmic_wrap.h | 15 PMIC_WRAP_PHASE_ALLINONE, enumerator
|
| H A D | spm_pmic_wrap.c | 58 .set[PMIC_WRAP_PHASE_ALLINONE] = {
|
| H A D | spm.c | 346 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); in spm_boot_init()
|