| /rk3399_ARM-atf/plat/renesas/rcar_gen4/ |
| H A D | plat_pm.c | 27 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
166 if (pwr_lvl != MPIDR_AFFLVL0) in rcar_validate_power_state()
169 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
171 for (i = MPIDR_AFFLVL0; i <= (uint64_t)pwr_lvl; i++) in rcar_validate_power_state()
191 for (i = MPIDR_AFFLVL0; i < (uint64_t)PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
194 for (i = MPIDR_AFFLVL0; i <= (uint64_t)PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/renesas/rcar_gen5/ |
| H A D | plat_pm.c | 26 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
170 if (pwr_lvl != MPIDR_AFFLVL0) { in rcar_validate_power_state()
174 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
176 for (i = MPIDR_AFFLVL0; i <= (uint64_t)pwr_lvl; i++) { in rcar_validate_power_state()
192 for (i = MPIDR_AFFLVL0; i <= (uint64_t)PLAT_MAX_PWR_LVL; i++) { in rcar_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/hisilicon/poplar/ |
| H A D | plat_pm.c | 76 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in poplar_pwr_domain_on_finish()
124 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in poplar_validate_power_state()
126 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()
151 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in poplar_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_pm.c | 24 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
167 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey_get_sys_suspend_power_state()
232 if (pwr_lvl != MPIDR_AFFLVL0) in hikey_validate_power_state()
235 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey_validate_power_state()
238 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in hikey_validate_power_state()
|
| /rk3399_ARM-atf/plat/renesas/common/ |
| H A D | plat_pm.c | 40 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
262 if (pwr_lvl != MPIDR_AFFLVL0) in rcar_validate_power_state()
265 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
267 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in rcar_validate_power_state()
286 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
293 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | imx8_psci.c | 43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
58 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_pm.c | 27 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
156 if (pwr_lvl != MPIDR_AFFLVL0) in hikey960_validate_power_state()
159 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey960_validate_power_state()
162 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in hikey960_validate_power_state()
293 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey960_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/qemu/qemu_sbsa/ |
| H A D | sbsa_pm.c | 62 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
65 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
183 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in qemu_pwr_domain_on_finish()
|
| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | plat_pm.c | 22 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
148 if (pwr_lvl != MPIDR_AFFLVL0) in rockchip_validate_power_state()
151 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in rockchip_validate_power_state()
154 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in rockchip_validate_power_state()
174 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rockchip_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/qemu/common/ |
| H A D | qemu_pm.c | 55 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
58 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
170 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in qemu_pwr_domain_on_finish()
|
| /rk3399_ARM-atf/plat/brcm/board/stingray/src/ |
| H A D | brcm_pm_ops.c | 29 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
362 if (pwr_lvl != MPIDR_AFFLVL0) in brcm_validate_power_state()
365 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in brcm_validate_power_state()
368 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in brcm_validate_power_state()
|
| H A D | pm.c | 63 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in brcm_pwr_domain_on_finish()
|
| /rk3399_ARM-atf/plat/nuvoton/npcm845x/ |
| H A D | npcm845x_psci.c | 57 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
65 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
193 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in npcm845x_pwr_domain_on_finish()
215 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in npcm845x_pwr_domain_suspend_finish()
|
| /rk3399_ARM-atf/plat/rpi/common/ |
| H A D | rpi3_pm.c | 69 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
72 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
175 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in rpi3_pwr_domain_on_finish()
|
| /rk3399_ARM-atf/plat/amlogic/axg/ |
| H A D | axg_pm.c | 102 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_on_finish()
117 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_off()
|
| /rk3399_ARM-atf/plat/ti/k3/common/ |
| H A D | k3_psci.c | 20 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
242 if (pwr_lvl != MPIDR_AFFLVL0) in k3_validate_power_state()
296 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in k3_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/xilinx/versal_net/ |
| H A D | plat_psci_pm.c | 320 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_net_validate_power_state()
322 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_net_validate_power_state()
343 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/imx/imx8m/include/ |
| H A D | imx8m_psci.h | 10 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
|
| /rk3399_ARM-atf/plat/imx/imx9/common/include/ |
| H A D | imx9_psci_common.h | 14 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
|
| /rk3399_ARM-atf/plat/amd/versal2/ |
| H A D | plat_psci_pm.c | 326 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal2_validate_power_state()
328 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal2_validate_power_state()
348 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in versal2_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/imx/imx8qm/include/ |
| H A D | platform_def.h | 26 #define IMX_PWR_LVL0 MPIDR_AFFLVL0
|
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/ |
| H A D | plat_psci_handlers.c | 55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; in tegra_soc_validate_power_state()
64 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; in tegra_soc_validate_power_state()
81 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in tegra_soc_validate_power_state()
201 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_suspend()
|
| /rk3399_ARM-atf/plat/qti/qcs615/inc/ |
| H A D | platform_def.h | 29 #define QTI_PWR_LVL0 MPIDR_AFFLVL0
|
| /rk3399_ARM-atf/plat/qti/sc7180/inc/ |
| H A D | platform_def.h | 28 #define QTI_PWR_LVL0 MPIDR_AFFLVL0
|
| /rk3399_ARM-atf/plat/qti/kodiak/inc/ |
| H A D | kodiak_def.h | 29 #define QTI_PWR_LVL0 MPIDR_AFFLVL0
|