Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_

Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`
chore(psci): drop skip_wfi variable
feat(arm): convert arm platforms to expect a wakeup
fix(cpus): avoid SME related loss of context on powerdown
feat(psci): allow cores to wake up from powerdown
refactor: panic after calling psci_power_down_wfi()
refactor(cpus): undo errata mitigations
feat(cpus): add sysreg_bit_toggle

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chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
e

chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
expectation so that future platform implementers don't get misled.

Change-Id: Ic33f0b6da74592ad6778fd802c2f0b85223af614
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(qemu): remove validate_ns_entrypoint" into integration

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This is not a problem when loading boot images as the
lower addresses are the same. However, it can be a problem when starting
up the secondary CPUs with a rather high non-secure entry point. So fix
this by removing the plat_psci_ops_t validate_ns_entrypoint assignment
to allow any non-secure entry point.

Change-Id: I95e92b71e0f4fa5f94444ea0cd2cb42e56faa472
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Merge "fix(plat/qemu): reboot/shutdown with low to high gpio" into integration

fix(plat/qemu): reboot/shutdown with low to high gpio

Use low to high gpio sequence to reboot/shutdown qemu machine.

Use low to high gpio pins level change which will cause an interrupt
in qemu vir

fix(plat/qemu): reboot/shutdown with low to high gpio

Use low to high gpio sequence to reboot/shutdown qemu machine.

Use low to high gpio pins level change which will cause an interrupt
in qemu virt platform. This change will supported with next qemu 6.1
release once patchset:
hw/arm: Make virt board secure powerdown/reset work
will be merged.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
CC: Peter Maydell <peter.maydell@linaro.org>
Change-Id: I70979517358c3b587722b2dcb33f63d29bf79d9b

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Merge "plat/qemu: trigger reboot with secure pl061" into integration

plat/qemu: trigger reboot with secure pl061

Secure pl061 qemu driver allows to rize the GPIO pin
from the secure world to reboot and power down
virtual machine.

Do not define secure-gpio for sbsa-r

plat/qemu: trigger reboot with secure pl061

Secure pl061 qemu driver allows to rize the GPIO pin
from the secure world to reboot and power down
virtual machine.

Do not define secure-gpio for sbsa-ref platform due to
reboot is done via sbsa-ec watchdog.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Change-Id: I508d7c5cf4c75cb169b34b00682a76f6761d3869

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Merge "qemu: Implement PSCI_CPU_OFF." into integration

qemu: Implement PSCI_CPU_OFF.

This is based on the rpi implementation from
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Ch

qemu: Implement PSCI_CPU_OFF.

This is based on the rpi implementation from
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1

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Merge changes I0fb7cf79,Ia8eb4710 into integration

* changes:
qemu: Implement qemu_system_off via semihosting.
qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.

qemu: Implement qemu_system_off via semihosting.

This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.

Sig

qemu: Implement qemu_system_off via semihosting.

This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03

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Merge changes from topic "qemu_sbsa" into integration

* changes:
qemu: Simplify the image size calculation
qemu: introducing sub-platforms to qemu platform

qemu: introducing sub-platforms to qemu platform

This commit change the plat/qemu directory structure into:

`-- plat
`-- qemu
|-- common (files shared with all qemu subplatforms)

qemu: introducing sub-platforms to qemu platform

This commit change the plat/qemu directory structure into:

`-- plat
`-- qemu
|-- common (files shared with all qemu subplatforms)
|-- qemu (original qemu platform)
|-- qemu_sbsa (new sqemu_sbsa platform)
|-- subplat1
`-- subplat2

This opens the possibility of adding new qemu sub-platforms which reuse
existing common platform code. The first platform which will leverage new
structure will be SBSA platform.

Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b

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