Home
last modified time | relevance | path

Searched refs:DRAM_BASE (Results 1 – 18 of 18) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx7/picopi/include/
H A Dplatform_def.h70 #define DRAM_BASE 0x80000000 macro
72 #define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
91 #define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
96 #define IMX_FIP_BASE (DRAM_BASE)
104 #define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
/rk3399_ARM-atf/plat/imx/imx7/warp7/include/
H A Dplatform_def.h72 #define DRAM_BASE 0x80000000 macro
74 #define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
93 #define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
98 #define IMX_FIP_BASE (DRAM_BASE)
106 #define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Dsocfpga_plat_def.h58 #define DRAM_BASE (0x0) macro
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dsocfpga_plat_def.h58 #define DRAM_BASE (0x0) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dsocfpga_plat_def.h74 #define DRAM_BASE (0x0) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dsocfpga_plat_def.h121 #define DRAM_BASE (0x80000000) macro
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl2_plat_setup.c36 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
H A Dbl31_plat_setup.c140 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dbl2_plat_setup.c40 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
H A Dbl31_plat_setup.c216 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
/rk3399_ARM-atf/plat/intel/soc/n5x/
H A Dbl31_plat_setup.c133 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c54 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
H A Dbl31_plat_setup.c195 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c396 zeromem((void *)DRAM_BASE, DRAM_SIZE); in configure_hmc_adaptor_regs()
H A Dagilex5_ddr.c406 ddr_info_set[0].start = DRAM_BASE; in agilex5_ddr_init()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c395 zeromem(DRAM_BASE, DRAM_SIZE); in configure_hmc_adaptor_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c407 zeromem(DRAM_BASE, DRAM_SIZE); in configure_hmc_adaptor_regs()
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_sip_svc.c311 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; in is_address_in_ddr_range()
799 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE);
800 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE);
801 *mem = *mem - DRAM_BASE;
803 *mem = *mem - DRAM_BASE;