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Searched refs:rate (Results 1 – 25 of 40) sorted by relevance

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/optee_os/core/drivers/scmi-msg/
H A Dclock.c53 unsigned long rate __unused) in plat_scmi_clock_set_rate()
163 unsigned long rate = 0; in scmi_clock_rate_get() local
180 rate = plat_scmi_clock_get_rate(msg->channel_id, clock_id); in scmi_clock_rate_get()
182 reg_pair_from_64(rate, return_values.rate + 1, return_values.rate); in scmi_clock_rate_get()
191 unsigned long rate = 0; in scmi_clock_rate_set() local
208 rate_64 = reg_pair_to_64(in_args->rate[1], in_args->rate[0]); in scmi_clock_rate_set()
209 rate = rate_64; in scmi_clock_rate_set()
211 status = plat_scmi_clock_set_rate(msg->channel_id, clock_id, rate); in scmi_clock_rate_set()
264 uint64_t rate = rates[n]; in write_rate_desc_array_in_buffer() local
266 reg_pair_from_64(rate, out + 2 * n + 1, out + 2 * n); in write_rate_desc_array_in_buffer()
[all …]
H A Dclock.h58 uint32_t rate[2]; member
86 uint32_t rate[2]; member
/optee_os/core/arch/riscv/kernel/
H A Dtee_time_rdtime.c40 uint64_t rate = read_cntfrq(); in tee_time_get_sys_time() local
42 time->seconds = tm / rate; in tee_time_get_sys_time()
43 time->millis = (tm % rate) / (rate / TEE_TIME_MILLIS_BASE); in tee_time_get_sys_time()
/optee_os/core/drivers/clk/sam/
H A Dat91_audio_pll.c189 static TEE_Result clk_audio_pll_frac_compute_frac(unsigned long rate, in clk_audio_pll_frac_compute_frac() argument
197 if (!rate || !parent_rate) in clk_audio_pll_frac_compute_frac()
200 tmp = rate; in clk_audio_pll_frac_compute_frac()
220 unsigned long rate, in clk_audio_pll_frac_set_rate() argument
228 if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX) in clk_audio_pll_frac_set_rate()
231 res = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr); in clk_audio_pll_frac_set_rate()
242 unsigned long rate, in clk_audio_pll_pad_set_rate() argument
248 if (!rate) in clk_audio_pll_pad_set_rate()
251 tmp_div = parent_rate / rate; in clk_audio_pll_pad_set_rate()
264 unsigned long rate, in clk_audio_pll_pmc_set_rate() argument
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H A Dat91_plldiv.c27 static TEE_Result clk_plldiv_set_rate(struct clk *clk, unsigned long rate, in clk_plldiv_set_rate() argument
32 if (parent_rate != rate && (parent_rate / 2 != rate)) in clk_plldiv_set_rate()
36 parent_rate != rate ? AT91_PMC_PLLADIV2 : 0); in clk_plldiv_set_rate()
H A Dat91_h32mx.c33 unsigned long rate, in clk_sama5d4_h32mx_set_rate() argument
39 if (parent_rate != rate && (parent_rate / 2) != rate) in clk_sama5d4_h32mx_set_rate()
42 if ((parent_rate / 2) == rate) in clk_sama5d4_h32mx_set_rate()
H A Dat91_master.c54 unsigned long rate = parent_rate; in clk_master_div_get_rate() local
65 rate /= charac->divisors[div]; in clk_master_div_get_rate()
67 if (rate < charac->output.min) in clk_master_div_get_rate()
69 else if (rate > charac->output.max) in clk_master_div_get_rate()
72 return rate; in clk_master_div_get_rate()
211 unsigned long rate, in clk_sama7g5_master_set_rate() argument
217 div = UDIV_ROUND_NEAREST(parent_rate, rate); in clk_sama7g5_master_set_rate()
247 unsigned long rate = parent_rate >> master->div; in clk_sama7g5_master_get_rate() local
250 rate = parent_rate / 3; in clk_sama7g5_master_get_rate()
252 return rate; in clk_sama7g5_master_get_rate()
H A Dat91_programmable.c38 unsigned long rate = 0; in clk_programmable_get_rate() local
41 rate = parent_rate / (PROG_PRES(layout, pckr) + 1); in clk_programmable_get_rate()
43 rate = parent_rate >> PROG_PRES(layout, pckr); in clk_programmable_get_rate()
45 return rate; in clk_programmable_get_rate()
93 static TEE_Result clk_programmable_set_rate(struct clk *clk, unsigned long rate, in clk_programmable_set_rate() argument
98 unsigned long div = parent_rate / rate; in clk_programmable_set_rate()
H A Dat91_pll.c115 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, in clk_pll_get_best_div_mul() argument
141 mindiv = (parent_rate * PLL_MUL_MIN) / rate; in clk_pll_get_best_div_mul()
158 maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate); in clk_pll_get_best_div_mul()
176 tmpmul = UDIV_ROUND_NEAREST(rate, parent_rate / tmpdiv); in clk_pll_get_best_div_mul()
178 if (tmprate > rate) in clk_pll_get_best_div_mul()
179 remainder = tmprate - rate; in clk_pll_get_best_div_mul()
181 remainder = rate - tmprate; in clk_pll_get_best_div_mul()
227 static TEE_Result clk_pll_set_rate(struct clk *clk, unsigned long rate, in clk_pll_set_rate() argument
236 ret = clk_pll_get_best_div_mul(pll, rate, parent_rate, in clk_pll_set_rate()
H A Dclk-sam9x60-pll.c185 unsigned long rate, in sam9x60_frac_pll_compute_mul_frac() argument
194 if (rate < frac->core.charac->output[0].min || in sam9x60_frac_pll_compute_mul_frac()
195 rate > frac->core.charac->output[0].max) in sam9x60_frac_pll_compute_mul_frac()
202 nmul = rate / parent_rate; in sam9x60_frac_pll_compute_mul_frac()
204 remainder = rate - tmprate; in sam9x60_frac_pll_compute_mul_frac()
228 unsigned long rate, in sam9x60_frac_pll_set_rate_chg() argument
236 ret = sam9x60_frac_pll_compute_mul_frac(frac, rate, parent_rate, true); in sam9x60_frac_pll_set_rate_chg()
353 unsigned long rate, in sam9x60_div_pll_set_rate() argument
358 if (parent_rate > rate) in sam9x60_div_pll_set_rate()
359 div->div = UDIV_ROUND_NEAREST(parent_rate, rate) - 1; in sam9x60_div_pll_set_rate()
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H A Dat91_usb.c59 unsigned long rate, in at91sam9x5_clk_usb_set_rate() argument
65 if (!rate) in at91sam9x5_clk_usb_set_rate()
68 div = UDIV_ROUND_NEAREST(parent_rate, rate); in at91sam9x5_clk_usb_set_rate()
H A Dat91_peripheral.c114 unsigned long rate, in clk_sam9x5_peripheral_set_rate() argument
121 if (parent_rate == rate) in clk_sam9x5_peripheral_set_rate()
127 if (periph->range.max && rate > periph->range.max) in clk_sam9x5_peripheral_set_rate()
131 if (parent_rate >> shift == rate) { in clk_sam9x5_peripheral_set_rate()
H A Dat91_cpu_opp.c47 static TEE_Result cpu_opp_clk_set_rate(struct clk *clk, unsigned long rate, in cpu_opp_clk_set_rate() argument
55 if (rate == opp_rates->rates[n]) in cpu_opp_clk_set_rate()
60 return clk->parent->ops->set_rate(clk->parent, rate, parent_rate); in cpu_opp_clk_set_rate()
H A Dat91_generated.c99 static TEE_Result clk_generated_set_rate(struct clk *clk, unsigned long rate, in clk_generated_set_rate() argument
105 if (!rate) in clk_generated_set_rate()
108 if (gck->range.max && rate > gck->range.max) in clk_generated_set_rate()
111 div = UDIV_ROUND_NEAREST(parent_rate, rate); in clk_generated_set_rate()
/optee_os/core/arch/arm/dts/
H A Dstm32mp15-pinctrl.dtsi43 slew-rate = <0>;
58 slew-rate = <0>;
166 slew-rate = <2>;
172 slew-rate = <0>;
217 slew-rate = <2>;
223 slew-rate = <0>;
268 slew-rate = <2>;
274 slew-rate = <0>;
317 slew-rate = <2>;
349 slew-rate = <1>;
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H A Dstm32mp13-pinctrl.dtsi15 slew-rate = <0>;
24 slew-rate = <1>;
33 slew-rate = <0>;
47 slew-rate = <0>;
H A Dstm32mp25-pinctrl.dtsi14 slew-rate = <0>;
27 slew-rate = <0>;
/optee_os/core/drivers/clk/
H A Dclk.c80 parent_rate = clk->parent->rate; in clk_compute_rate_no_lock()
84 clk->rate = clk->ops->get_rate(clk, parent_rate); in clk_compute_rate_no_lock()
86 clk->rate = parent_rate; in clk_compute_rate_no_lock()
209 return clk->rate; in clk_get_rate()
212 static TEE_Result clk_set_rate_no_lock(struct clk *clk, unsigned long rate) in clk_set_rate_no_lock() argument
222 res = clk_set_rate_no_lock(clk->parent, rate); in clk_set_rate_no_lock()
225 rate = clk_get_rate(clk->parent); in clk_set_rate_no_lock()
235 res = clk->ops->set_rate(clk, rate, parent_rate); in clk_set_rate_no_lock()
249 TEE_Result clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
258 res = clk_set_rate_no_lock(clk, rate); in clk_set_rate()
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H A Dfixed_clk.c13 unsigned long rate; member
21 return d->rate; in fixed_clk_get_rate()
57 fcd->rate = fdt32_to_cpu(*freq); in fixed_clock_probe()
H A Dclk-stm32-core.h54 unsigned long rate; member
133 TEE_Result stm32_div_set_rate(int div_id, unsigned long rate,
146 unsigned long rate,
153 TEE_Result clk_stm32_composite_set_rate(struct clk *clk, unsigned long rate,
174 .rate = (_rate),\
H A Dclk-stm32-core.c270 static int divider_get_val(unsigned long rate, unsigned long parent_rate, in divider_get_val() argument
277 div = UDIV_ROUND_NEAREST((uint64_t)parent_rate, rate); in divider_get_val()
335 TEE_Result stm32_div_set_rate(int div_id, unsigned long rate, in stm32_div_set_rate() argument
342 value = divider_get_val(rate, prate, divider->table, in stm32_div_set_rate()
423 unsigned long rate, in clk_stm32_divider_set_rate() argument
428 return stm32_div_set_rate(cfg->div_id, rate, parent_rate); in clk_stm32_divider_set_rate()
470 TEE_Result clk_stm32_composite_set_rate(struct clk *clk, unsigned long rate, in clk_stm32_composite_set_rate() argument
478 return stm32_div_set_rate(cfg->div_id, rate, parent_rate); in clk_stm32_composite_set_rate()
555 unsigned long long rate = (unsigned long long)parent_rate * d->mult; in fixed_factor_get_rate() local
560 return (unsigned long)(rate / d->div); in fixed_factor_get_rate()
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H A Dclk_dt.c147 unsigned long rate = 0; in parse_assigned_clock() local
175 rate = fdt32_to_cpu(rate_prop[clock_idx]); in parse_assigned_clock()
176 if (rate && clk_set_rate(clk, rate) != TEE_SUCCESS) in parse_assigned_clock()
/optee_os/lib/libutee/arch/arm/gprof/
H A Dgprof_pta.c69 TEE_Result __pta_gprof_pc_sampling_stop(uint32_t *rate) in __pta_gprof_pc_sampling_stop() argument
84 if (rate) in __pta_gprof_pc_sampling_stop()
85 *rate = params[0].value.a; in __pta_gprof_pc_sampling_stop()
/optee_os/core/include/drivers/
H A Dclk.h41 unsigned long rate; member
84 TEE_Result (*set_rate)(struct clk *clk, unsigned long rate,
150 TEE_Result clk_set_rate(struct clk *clk, unsigned long rate);
/optee_os/core/pta/
H A Dgprof.c116 uint32_t rate = 0; in gprof_stop_pc_sampling() local
130 rate = ((uint64_t)sbuf->count * sbuf->freq) / sbuf->usr; in gprof_stop_pc_sampling()
131 params[0].value.a = rate; in gprof_stop_pc_sampling()
135 sbuf->freq, rate); in gprof_stop_pc_sampling()

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