| #
33da0db4 |
| 17-Sep-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
dts: stm32: refine STM32MP25 secure/non-secure USART2 pinctrl states
Explicitly state that legacy pinctrl phandles usart2_pins_a refer to non-secure USART2 pin muxing, used in STM32MP23 and STM32MP2
dts: stm32: refine STM32MP25 secure/non-secure USART2 pinctrl states
Explicitly state that legacy pinctrl phandles usart2_pins_a refer to non-secure USART2 pin muxing, used in STM32MP23 and STM32MP25 based boards for OP-TEE console using a non-secure UART bus.
Define secure USART2 bus pinctrl states for board that needs to use the USART2 bus in secure state.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| #
6d20c119 |
| 28-Aug-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
dts: stm32: add console support on USART2 for stm32mp257f-ev1
Populate USART2 node and enable console support on USART2 on stm32mp257f-ev1 board.
Signed-off-by: Gatien Chevallier <gatien.chevallier
dts: stm32: add console support on USART2 for stm32mp257f-ev1
Populate USART2 node and enable console support on USART2 on stm32mp257f-ev1 board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
8854076a |
| 30-Oct-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
dts: stm32: introduce STM32MP25 SoCs family
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*cortex-A35, common peripherals like SDMMC, UART, SPI,
dts: stm32: introduce STM32MP25 SoCs family
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ...
-STM32MP253: STM32MP251 + 1*cortex-A35 (dual CPU), a second ETH, CAN-FD and LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode. -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/ A35 frequency: -STM32MP25xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot.
Available packages are:
STM32MP25xAI: 18*18/FCBGA 172 ios STM32MP25xAK: 14*14/FCBGA 144 ios STM32MP25xAL: 10*10/TFBGA 144 ios
More information available at: Link: https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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