140cc9401SGatien Chevallier// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 240cc9401SGatien Chevallier/* 340cc9401SGatien Chevallier * Copyright (C) STMicroelectronics 2019-2022 - All Rights Reserved 440cc9401SGatien Chevallier * Author: Alexandre Torgue <alexandre.torgue@st.com> 540cc9401SGatien Chevallier */ 640cc9401SGatien Chevallier#include <dt-bindings/pinctrl/stm32-pinfunc.h> 740cc9401SGatien Chevallier 840cc9401SGatien Chevallier&pinctrl { 940cc9401SGatien Chevallier i2c4_pins_a: i2c4-0 { 1040cc9401SGatien Chevallier pins { 1140cc9401SGatien Chevallier pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */ 1240cc9401SGatien Chevallier <STM32_PINMUX('B', 9, AF6)>; /* I2C4_SDA */ 1340cc9401SGatien Chevallier bias-disable; 1440cc9401SGatien Chevallier drive-open-drain; 1540cc9401SGatien Chevallier slew-rate = <0>; 1640cc9401SGatien Chevallier }; 1740cc9401SGatien Chevallier }; 1840cc9401SGatien Chevallier 19f55e624aSEtienne Carriere rcc_mco_pins_a: rcc-pins-0 { 20f55e624aSEtienne Carriere pins { 21f55e624aSEtienne Carriere pinmux = <STM32_PINMUX('D', 7, AF0)>; /* RCC_MCO_1 */ 22f55e624aSEtienne Carriere bias-disable; 23f55e624aSEtienne Carriere drive-push-pull; 24f55e624aSEtienne Carriere slew-rate = <1>; 25f55e624aSEtienne Carriere }; 26f55e624aSEtienne Carriere }; 27f55e624aSEtienne Carriere 2840cc9401SGatien Chevallier uart4_pins_a: uart4-0 { 2940cc9401SGatien Chevallier pins1 { 30*0ffc3e3eSEtienne Carriere pinmux = <STM32_PINMUX_NSEC('D', 6, AF8)>; /* UART4_TX */ 3140cc9401SGatien Chevallier bias-disable; 3240cc9401SGatien Chevallier drive-push-pull; 3340cc9401SGatien Chevallier slew-rate = <0>; 3440cc9401SGatien Chevallier }; 3540cc9401SGatien Chevallier pins2 { 36*0ffc3e3eSEtienne Carriere pinmux = <STM32_PINMUX_NSEC('D', 8, AF8)>; /* UART4_RX */ 3740cc9401SGatien Chevallier bias-disable; 3840cc9401SGatien Chevallier }; 3940cc9401SGatien Chevallier }; 4040cc9401SGatien Chevallier 4140cc9401SGatien Chevallier usart1_pins_a: usart1-0 { 4240cc9401SGatien Chevallier pins1 { 4340cc9401SGatien Chevallier pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ 4440cc9401SGatien Chevallier <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ 4540cc9401SGatien Chevallier bias-disable; 4640cc9401SGatien Chevallier drive-push-pull; 4740cc9401SGatien Chevallier slew-rate = <0>; 4840cc9401SGatien Chevallier }; 4940cc9401SGatien Chevallier pins2 { 5040cc9401SGatien Chevallier pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */ 5140cc9401SGatien Chevallier <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */ 5240cc9401SGatien Chevallier bias-pull-up; 5340cc9401SGatien Chevallier }; 5440cc9401SGatien Chevallier }; 5540cc9401SGatien Chevallier}; 56