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Searched refs:CORE_MMU_PGDIR_SIZE (Results 1 – 25 of 44) sorted by relevance

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/optee_os/core/arch/arm/plat-imx/
H A Dmain.c46 CORE_MMU_PGDIR_SIZE);
49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE);
59 ROUNDUP(AIPS0_SIZE, CORE_MMU_PGDIR_SIZE));
63 ROUNDUP(AIPS1_SIZE, CORE_MMU_PGDIR_SIZE));
67 ROUNDUP(AIPS2_SIZE, CORE_MMU_PGDIR_SIZE));
71 ROUNDUP(AIPS3_SIZE, CORE_MMU_PGDIR_SIZE));
75 ROUNDDOWN(IRAM_BASE, CORE_MMU_PGDIR_SIZE),
76 CORE_MMU_PGDIR_SIZE);
83 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE),
[all …]
H A Dimx_pl310.c25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
26 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-sprd/
H A Dmain.c37 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
38 CORE_MMU_PGDIR_SIZE);
41 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
42 CORE_MMU_PGDIR_SIZE);
45 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
46 CORE_MMU_PGDIR_SIZE);
H A Dplatform_config.h84 CORE_MMU_PGDIR_SIZE)
86 CORE_MMU_PGDIR_SIZE)
/optee_os/core/arch/arm/plat-uniphier/
H A Dmain.c18 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
19 CORE_MMU_PGDIR_SIZE);
22 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
23 CORE_MMU_PGDIR_SIZE);
26 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
27 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-zynqmp/
H A Dmain.c52 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
53 CORE_MMU_PGDIR_SIZE);
56 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
57 CORE_MMU_PGDIR_SIZE);
60 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
61 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-poplar/
H A Dplatform_config.h124 #define TA_RAM_START ROUNDUP(TZDRAM_BASE, CORE_MMU_PGDIR_SIZE)
125 #define TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_PGDIR_SIZE)
135 CORE_MMU_PGDIR_SIZE)
138 CORE_MMU_PGDIR_SIZE)
/optee_os/core/arch/arm/plat-versal/
H A Dmain.c31 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
32 CORE_MMU_PGDIR_SIZE);
35 GIC_BASE, CORE_MMU_PGDIR_SIZE);
38 GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-synquacer/
H A Dmain.c26 CORE_MMU_PGDIR_SIZE);
27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
29 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-marvell/
H A Dmain.c62 CORE_MMU_PGDIR_SIZE);
69 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, CORE_MMU_PGDIR_SIZE);
71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-mediatek/
H A Dmain.c26 CORE_MMU_PGDIR_SIZE);
28 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-versal2/
H A Dmain.c26 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
27 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-zynq7k/
H A Dmain.c50 CORE_MMU_PGDIR_SIZE);
51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-bcm/
H A Dplatform_config.h55 #define BCM_DEVICE0_SIZE CORE_MMU_PGDIR_SIZE
57 #define BCM_DEVICE1_SIZE CORE_MMU_PGDIR_SIZE
/optee_os/core/arch/riscv/include/mm/
H A Dgeneric_ram_layout.h123 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE
158 #define TA_RAM_START ROUNDUP(TDDRAM_BASE, CORE_MMU_PGDIR_SIZE)
/optee_os/core/arch/arm/plat-ls/
H A Dmain.c60 CORE_MMU_PGDIR_SIZE);
62 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
72 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, DCFG_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-ti/
H A Dplatform_config.h135 CORE_MMU_PGDIR_SIZE)
138 CORE_MMU_PGDIR_SIZE)
/optee_os/core/mm/
H A Dpgt_cache.c167 return core_is_buffer_inside(p->vabase, CORE_MMU_PGDIR_SIZE, begin, in pgt_entry_matches()
241 vaddr_t e = MIN(p->vabase + CORE_MMU_PGDIR_SIZE, end); in pgt_clear_range()
291 for (va = ROUNDDOWN(r->va, CORE_MMU_PGDIR_SIZE); in pgt_check_avail()
292 va < r->va + r->size; va += CORE_MMU_PGDIR_SIZE) { in pgt_check_avail()
315 for (va = ROUNDDOWN(r->va, CORE_MMU_PGDIR_SIZE); in pgt_check_avail()
316 va < r->va + r->size; va += CORE_MMU_PGDIR_SIZE) { in pgt_check_avail()
667 if (!core_is_buffer_inside(p->vabase, CORE_MMU_PGDIR_SIZE, begin, in pgt_entry_matches()
746 vaddr_t e = MIN(p->vabase + CORE_MMU_PGDIR_SIZE, end); in clear_ctx_range_from_list()
782 for (va = ROUNDDOWN(r->va, CORE_MMU_PGDIR_SIZE); in pgt_alloc_unlocked()
783 va < r->va + r->size; va += CORE_MMU_PGDIR_SIZE) { in pgt_alloc_unlocked()
[all …]
/optee_os/core/arch/arm/plat-rzn1/
H A Dmain.c33 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
34 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/include/mm/
H A Dcore_mmu.h30 #define CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT) macro
31 #define CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1)
46 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE
217 __register_memory(#addr, type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \
219 ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \
220 CORE_MMU_PGDIR_SIZE), phys_mem_map)
/optee_os/core/arch/arm/plat-amlogic/
H A Dmain.c14 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-sam/
H A Dsam_sfr.c18 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SFR_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/drivers/
H A Dimx_caam.c33 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CAAM_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/riscv/plat-virt/
H A Dmain.c17 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART0_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/include/mm/
H A Dgeneric_ram_layout.h122 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE

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