core: mm: replace MEM_AREA_TA_RAM

Replace MEM_AREA_TA_RAM with MEM_AREA_SEC_RAM_OVERALL.

All read/write secure memory is covered by MEM_AREA_SEC_RAM_OVERALL,
sometimes using an aliased map. But sec

core: mm: replace MEM_AREA_TA_RAM

Replace MEM_AREA_TA_RAM with MEM_AREA_SEC_RAM_OVERALL.

All read/write secure memory is covered by MEM_AREA_SEC_RAM_OVERALL,
sometimes using an aliased map. But secure read-only or execute core
memory is not covered as that would defeat the purpose of
CFG_CORE_RWDATA_NOEXEC.

Since the partition TA memory isn't accessed via MEM_AREA_TA_RAM any
longer, don't map it using the partition specific map.

This is needed later where unification of OP-TEE core and physical TA
memory is possible.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: replace tee_mm_sec_ddr with phys_mem functions

Replace the tee_mm_sec_ddr mm pool with the phys_mem functions. This
doesn't change the behaviour.

Signed-off-by: Jens Wiklander <jens.wiklander

core: replace tee_mm_sec_ddr with phys_mem functions

Replace the tee_mm_sec_ddr mm pool with the phys_mem functions. This
doesn't change the behaviour.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: add CFG_PGT_CACHE_ENTRIES

Add CFG_PGT_CACHE_ENTRIES to allow platforms to customize the page
table cache size. This is needed for example when a platform is to
support very large TAs of se

core: mm: add CFG_PGT_CACHE_ENTRIES

Add CFG_PGT_CACHE_ENTRIES to allow platforms to customize the page
table cache size. This is needed for example when a platform is to
support very large TAs of several dozen of Mbytes of private memory
(code/data).

Move PGT_CACHE_SIZE macro definition from pgt_cache.h to pgt_cache.c
since it is used only in that source file.

By the way, fix pgt_cache.h layout to have header files includes first
followed by macro definitions.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: move pgt_cache.c to core/mm

This commit moves core/arch/arm/mm/pgt_cache.c to core/mm/pgt_cache.c
The implementation can be used by other architectures.
The commit does not rename CFG_CORE

core: mm: move pgt_cache.c to core/mm

This commit moves core/arch/arm/mm/pgt_cache.c to core/mm/pgt_cache.c
The implementation can be used by other architectures.
The commit does not rename CFG_CORE_PREALLOC_EL0_TBLS flag and other
depending flags (CFG_WITH_PAGER, CFG_WITH_LPAE). Therefore, an
architecture implementation may set or not these flags.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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