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Searched refs:reg_read (Results 1 – 25 of 223) sorted by relevance

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/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c75 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
133 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
142 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
149 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
183 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in ddr3_dfs_high_2_low()
188 reg = reg_read(REG_REGISTERED_DRAM_CTRL_ADDR); in ddr3_dfs_high_2_low()
198 reg = reg_read(REG_DDR3_MR1_CS_ADDR + in ddr3_dfs_high_2_low()
207 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
213 reg = ((reg_read(REG_DFS_ADDR)) & (1 << REG_DFS_ATSR_OFFS)); in ddr3_dfs_high_2_low()
220 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_high_2_low()
[all …]
H A Dddr3_write_leveling.c76 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
90 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
96 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_write_leveling_hw()
100 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_write_leveling_hw()
163 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR) | in ddr3_write_leveling_hw()
219 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_wl_supplement()
252 (reg_read(REG_DRAM_TRAINING_2_ADDR) in ddr3_wl_supplement()
401 (reg_read(REG_DRAM_TRAINING_2_ADDR) in ddr3_wl_supplement()
451 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_wl_supplement()
456 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_wl_supplement()
[all …]
H A Dddr3_init.c72 printf("0x%08x = 0x%08x\n", reg, reg_read(reg)); in debug_print_reg()
227 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
378 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> in ddr3_init_main()
395 reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25)); in ddr3_init_main()
453 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in ddr3_init_main()
474 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
496 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
513 reg = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_init_main()
539 if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) & in ddr3_init_main()
572 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL); in ddr3_init_main()
[all …]
H A Dddr3_read_leveling.c79 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_read_leveling_hw()
85 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_read_leveling_hw()
90 if (reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_read_leveling_hw()
152 reg_read(REG_READ_DATA_READY_DELAYS_ADDR) & in ddr3_read_leveling_hw()
155 reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR) & in ddr3_read_leveling_hw()
189 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
208 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
220 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_sw()
228 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_read_leveling_sw()
299 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
[all …]
H A Dddr3_hw_training.c106 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
115 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
124 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_hw_training()
130 reg = reg_read(REG_DDR3_MR0_ADDR) >> 2; in ddr3_hw_training()
132 reg = reg_read(REG_DDR3_MR0_CS_ADDR) >> 2; in ddr3_hw_training()
140 reg = reg_read(REG_DDR3_MR2_ADDR) >> REG_DDR3_MR2_CWL_OFFS; in ddr3_hw_training()
142 reg = reg_read(REG_DDR3_MR2_CS_ADDR) >> REG_DDR3_MR2_CWL_OFFS; in ddr3_hw_training()
171 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS)) in ddr3_hw_training()
519 reg = reg_read(REG_SDRAM_TIMING_HIGH_ADDR); in ddr3_set_performance_params()
568 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_write_pup_reg()
[all …]
H A Dxor.c28 xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0)); in mv_sys_xor_init()
30 xor_regs_base_backup[ui] = reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
32 xor_regs_mask_backup[ui] = reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
146 val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) in mv_xor_ctrl_set()
172 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
262 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_transfer()
352 state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_state_get()
H A Dddr3_pbs.c109 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_tx()
160 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
286 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
382 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_tx()
387 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_pbs_tx()
552 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_rx()
602 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_rx()
674 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_pbs_rx()
680 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_rx()
688 reg = (reg_read(REG_DRAM_TRAINING_2_ADDR)) in ddr3_pbs_rx()
[all …]
/OK3568_Linux_fs/kernel/arch/x86/pci/
H A Dce4100.c61 static void reg_read(struct sim_dev_reg *reg, u32 *value) in reg_read() function
81 reg_read(reg, value); in ehci_reg_read()
94 reg_read(reg, value); in sata_revid_read()
104 DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
105 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
106 DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
107 DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
108 DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
109 DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
110 DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c143 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0) in board_modules_scan()
175 sar = reg_read(MPP_SAMPLE_AT_RESET(0)); in board_cpu_freq_get()
176 sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1)); in board_cpu_freq_get()
285 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in serdes_phy_config()
305 cpu_avs = reg_read(CPU_AVS_CONTROL2_REG); in serdes_phy_config()
312 tmp2 = reg_read(CPU_AVS_CONTROL0_REG); in serdes_phy_config()
320 fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) & in serdes_phy_config()
325 core_avs = reg_read(CORE_AVS_CONTROL_0REG); in serdes_phy_config()
337 core_avs = reg_read(CORE_AVS_CONTROL_2REG); in serdes_phy_config()
343 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_phy_config()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dctrl_pex.c45 tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx)); in hws_pex_config()
51 tmp = reg_read(SOC_CTRL_REG); in hws_pex_config()
113 tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx)); in hws_pex_config()
124 temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS in hws_pex_config()
130 temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS( in hws_pex_config()
172 tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx)); in hws_pex_config()
180 tmp = reg_read(PEX_CTRL_REG(pex_idx)); in hws_pex_config()
216 dev_id = reg_read(PEX_CFG_DIRECT_ACCESS in hws_pex_config()
240 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_local_bus_num_set()
255 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_local_dev_num_set()
[all …]
H A Dsys_env_lib.c63 value = (reg_read(DEVICE_SAMPLE_AT_RESET1_REG) >> 15) & 0x1; in mv_board_tclk_get()
124 reg = reg_read(MPP_CONTROL_REG(MPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
130 reg = reg_read(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
138 reg = reg_read(GPP_DATA_IN_REG(GPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
194 u32 default_ctrl_id, ctrl_id = reg_read(DEV_ID_REG); in sys_env_model_get()
232 g_dev_id = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); in sys_env_device_id_get()
/OK3568_Linux_fs/kernel/sound/i2c/other/
H A Dak4117.c32 static inline unsigned char reg_read(struct ak4117 *ak4117, unsigned char reg) in reg_read() function
44 …printk(KERN_DEBUG "reg[%02x] = %02x (%02x)\n", i, reg_read(ak4117, i), i < sizeof(ak4117->regmap) …
85 chip->rcs0 = reg_read(chip, AK4117_REG_RCS0) & ~(AK4117_QINT | AK4117_CINT | AK4117_STC); in snd_ak4117_create()
86 chip->rcs1 = reg_read(chip, AK4117_REG_RCS1); in snd_ak4117_create()
87 chip->rcs2 = reg_read(chip, AK4117_REG_RCS2); in snd_ak4117_create()
175 ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; in snd_ak4117_in_bit_get()
229 ucontrol->value.integer.value[0] = external_rate(reg_read(chip, AK4117_REG_RCS1)); in snd_ak4117_rate_get()
247 ucontrol->value.iec958.status[i] = reg_read(chip, AK4117_REG_RXCSB0 + i); in snd_ak4117_spdif_get()
282 tmp = reg_read(chip, AK4117_REG_Pc0) | (reg_read(chip, AK4117_REG_Pc1) << 8); in snd_ak4117_spdif_pget()
284 tmp = reg_read(chip, AK4117_REG_Pd0) | (reg_read(chip, AK4117_REG_Pd1) << 8); in snd_ak4117_spdif_pget()
[all …]
H A Dak4113.c37 static inline unsigned char reg_read(struct ak4113 *ak4113, unsigned char reg) in reg_read() function
83 chip->rcs0 = reg_read(chip, AK4113_REG_RCS0) & ~(AK4113_QINT | in snd_ak4113_create()
85 chip->rcs1 = reg_read(chip, AK4113_REG_RCS1); in snd_ak4113_create()
86 chip->rcs2 = reg_read(chip, AK4113_REG_RCS2); in snd_ak4113_create()
207 ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; in snd_ak4113_in_bit_get()
264 ucontrol->value.integer.value[0] = external_rate(reg_read(chip, in snd_ak4113_rate_get()
284 ucontrol->value.iec958.status[i] = reg_read(chip, in snd_ak4113_spdif_get()
322 tmp = reg_read(chip, AK4113_REG_Pc0) | in snd_ak4113_spdif_pget()
323 (reg_read(chip, AK4113_REG_Pc1) << 8); in snd_ak4113_spdif_pget()
325 tmp = reg_read(chip, AK4113_REG_Pd0) | in snd_ak4113_spdif_pget()
[all …]
H A Dak4114.c36 static inline unsigned char reg_read(struct ak4114 *ak4114, unsigned char reg) in reg_read() function
48 …printk(KERN_DEBUG "reg[%02x] = %02x (%02x)\n", i, reg_read(ak4114, i), i < ARRAY_SIZE(ak4114->regm…
97 chip->rcs0 = reg_read(chip, AK4114_REG_RCS0) & ~(AK4114_QINT | AK4114_CINT); in snd_ak4114_create()
98 chip->rcs1 = reg_read(chip, AK4114_REG_RCS1); in snd_ak4114_create()
201 ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; in snd_ak4114_in_bit_get()
220 ucontrol->value.integer.value[0] = external_rate(reg_read(chip, AK4114_REG_RCS1)); in snd_ak4114_rate_get()
238 ucontrol->value.iec958.status[i] = reg_read(chip, AK4114_REG_RXCSB0 + i); in snd_ak4114_spdif_get()
295 tmp = reg_read(chip, AK4114_REG_Pc0) | (reg_read(chip, AK4114_REG_Pc1) << 8); in snd_ak4114_spdif_pget()
297 tmp = reg_read(chip, AK4114_REG_Pd0) | (reg_read(chip, AK4114_REG_Pd1) << 8); in snd_ak4114_spdif_pget()
316 ucontrol->value.bytes.data[i] = reg_read(chip, AK4114_REG_QSUB_ADDR + i); in snd_ak4114_spdif_qget()
[all …]
/OK3568_Linux_fs/kernel/drivers/base/regmap/
H A Dregmap-mmio.c25 unsigned int (*reg_read)(struct regmap_mmio_context *ctx, member
183 *val = ctx->reg_read(ctx, reg); in regmap_mmio_read()
206 .reg_read = regmap_mmio_read,
250 ctx->reg_read = regmap_mmio_read8; in regmap_mmio_gen_context()
254 ctx->reg_read = regmap_mmio_read16le; in regmap_mmio_gen_context()
258 ctx->reg_read = regmap_mmio_read32le; in regmap_mmio_gen_context()
263 ctx->reg_read = regmap_mmio_read64le; in regmap_mmio_gen_context()
278 ctx->reg_read = regmap_mmio_read8; in regmap_mmio_gen_context()
282 ctx->reg_read = regmap_mmio_read16be; in regmap_mmio_gen_context()
286 ctx->reg_read = regmap_mmio_read32be; in regmap_mmio_gen_context()
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c131 value = reg_read(DEV_VERSION_ID_REG); in sys_env_device_rev_get()
174 return reg_read(REG_DDR3_RANK_CTRL_ADDR) & in sys_env_get_cs_ena_from_reg()
240 win[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
304 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> in ddr3_init()
332 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in ddr3_init()
343 reg = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_init()
405 reg = reg_read(REG_BOOTROM_ROUTINE_ADDR); in ddr3_init()
461 reg = reg_read(reg_addr); in ddr3_get_static_mc_value()
573 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL); in ddr3_new_tip_dlb_config()
664 bus_width = (reg_read(REG_SDRAM_CONFIG_ADDR) & 0x8000) >> in ddr3_get_bus_width()
[all …]
H A Dxor.c32 ui_xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0)); in mv_sys_xor_init()
35 reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
38 reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
148 old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) & in mv_xor_ctrl_set()
174 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
242 state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_state_get()
H A Dddr3_a38x.c209 if ((reg_read(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0) in ddr3_ctrl_get_junc_temp()
214 if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) { in ddr3_ctrl_get_junc_temp()
219 reg = reg_read(TSEN_STATUS_REG); in ddr3_ctrl_get_junc_temp()
313 *data = reg_read(reg_addr) & mask; in ddr3_tip_a38x_if_read()
330 reg = reg_read(CS_ENABLE_REG); in ddr3_tip_a38x_select_ddr_controller()
483 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_get_init_freq()
534 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_get_medium_freq()
602 sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_set_divider()
/OK3568_Linux_fs/u-boot/board/micronas/vct/
H A Dtop.c39 reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE)); in top_read_pin()
42 reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE)); in top_read_pin()
45 reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE)); in top_read_pin()
48 reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE)); in top_read_pin()
57 reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + in top_read_pin()
61 reg.reg = reg_read(TOP_BASE + (pin * 4)); in top_read_pin()
131 reg.reg = reg_read(TOP_BASE + (pin * 4)); in top_set_pin()
H A Ddcgu.c35 en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); in dcgu_set_clk_switch()
37 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); in dcgu_set_clk_switch()
121 en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); in dcgu_set_clk_switch()
124 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); in dcgu_set_clk_switch()
148 val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE)); in dcgu_set_reset_switch()
/OK3568_Linux_fs/kernel/drivers/firewire/
H A Dinit_ohci1394_dma.c45 static inline u32 reg_read(const struct ohci *ohci, int offset) in reg_read() function
61 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000) in get_phy_reg()
65 r = reg_read(ohci, OHCI1394_PhyControl); in get_phy_reg()
78 if (!(reg_read(ohci, OHCI1394_PhyControl) & 0x00004000)) in set_phy_reg()
92 if (!(reg_read(ohci, OHCI1394_HCControlSet) in init_ohci1394_soft_reset()
110 bus_options = reg_read(ohci, OHCI1394_BusOptions); in init_ohci1394_initialize()
183 events = reg_read(ohci, OHCI1394_IntEventSet); in init_ohci1394_wait_for_busresets()
/OK3568_Linux_fs/kernel/drivers/media/pci/tw686x/
H A Dtw686x-core.c95 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); in tw686x_disable_channel()
96 u32 dma_cmd = reg_read(dev, DMA_CMD); in tw686x_disable_channel()
114 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); in tw686x_enable_channel()
115 u32 dma_cmd = reg_read(dev, DMA_CMD); in tw686x_enable_channel()
145 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); in tw686x_reset_channels()
146 dma_cmd = reg_read(dev, DMA_CMD); in tw686x_reset_channels()
173 int_status = reg_read(dev, INT_STATUS); /* cleared on read */ in tw686x_irq()
174 fifo_status = reg_read(dev, VIDEO_FIFO_STATUS); in tw686x_irq()
188 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); in tw686x_irq()
200 pb_status = reg_read(dev, PB_STATUS); in tw686x_irq()
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dak881x.c35 static int reg_read(struct i2c_client *client, const u8 reg) in reg_read() function
49 int ret = reg_read(client, reg); in reg_set()
70 reg->val = reg_read(client, reg->reg); in ak881x_g_register()
193 reg_read(client, AK881X_STATUS)); in ak881x_s_stream()
198 reg_read(client, AK881X_STATUS)); in ak881x_s_stream()
248 data = reg_read(client, AK881X_DEVICE_ID); in ak881x_probe()
260 ak881x->revision = reg_read(client, AK881X_DEVICE_REVISION); in ak881x_probe()
/OK3568_Linux_fs/kernel/drivers/media/usb/gspca/
H A Dspca508.c1250 static int reg_read(struct gspca_dev *gspca_dev, in reg_read() function
1297 ret = reg_read(gspca_dev, 0x8803); in ssi_w()
1358 data1 = reg_read(gspca_dev, 0x8104); in sd_config()
1359 data2 = reg_read(gspca_dev, 0x8105); in sd_config()
1363 data1 = reg_read(gspca_dev, 0x8106); in sd_config()
1364 data2 = reg_read(gspca_dev, 0x8107); in sd_config()
1368 data1 = reg_read(gspca_dev, 0x8621); in sd_config()
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/
H A Ddram.c122 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, in mv_xor_init2()
124 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, in mv_xor_init2()
126 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, in mv_xor_init2()
177 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
207 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
214 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) in ecc_enabled()

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