1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Original Author Guenter Gebhardt
5*4882a593Smuzhiyun * Copyright (C) 2006 Micronas GmbH
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <linux/errno.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "vct.h"
14*4882a593Smuzhiyun
dcgu_set_clk_switch(enum dcgu_hw_module module,enum dcgu_switch setup)15*4882a593Smuzhiyun int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun u32 enable;
18*4882a593Smuzhiyun union dcgu_clk_en1 en1;
19*4882a593Smuzhiyun union dcgu_clk_en2 en2;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun switch (setup) {
22*4882a593Smuzhiyun case DCGU_SWITCH_ON:
23*4882a593Smuzhiyun enable = 1;
24*4882a593Smuzhiyun break;
25*4882a593Smuzhiyun case DCGU_SWITCH_OFF:
26*4882a593Smuzhiyun enable = 0;
27*4882a593Smuzhiyun break;
28*4882a593Smuzhiyun default:
29*4882a593Smuzhiyun printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
30*4882a593Smuzhiyun setup);
31*4882a593Smuzhiyun return -EINVAL;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if (module == DCGU_HW_MODULE_CPU)
35*4882a593Smuzhiyun en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
36*4882a593Smuzhiyun else
37*4882a593Smuzhiyun en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun switch (module) {
40*4882a593Smuzhiyun case DCGU_HW_MODULE_MSMC:
41*4882a593Smuzhiyun en1.bits.en_clkmsmc = enable;
42*4882a593Smuzhiyun break;
43*4882a593Smuzhiyun case DCGU_HW_MODULE_SSI_S:
44*4882a593Smuzhiyun en1.bits.en_clkssi_s = enable;
45*4882a593Smuzhiyun break;
46*4882a593Smuzhiyun case DCGU_HW_MODULE_SSI_M:
47*4882a593Smuzhiyun en1.bits.en_clkssi_m = enable;
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun case DCGU_HW_MODULE_SMC:
50*4882a593Smuzhiyun en1.bits.en_clksmc = enable;
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun case DCGU_HW_MODULE_EBI:
53*4882a593Smuzhiyun en1.bits.en_clkebi = enable;
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case DCGU_HW_MODULE_USB_PLL:
56*4882a593Smuzhiyun en1.bits.en_usbpll = enable;
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun case DCGU_HW_MODULE_USB_60:
59*4882a593Smuzhiyun en1.bits.en_clkusb60 = enable;
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun case DCGU_HW_MODULE_USB_24:
62*4882a593Smuzhiyun en1.bits.en_clkusb24 = enable;
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun case DCGU_HW_MODULE_UART_2:
65*4882a593Smuzhiyun en1.bits.en_clkuart2 = enable;
66*4882a593Smuzhiyun break;
67*4882a593Smuzhiyun case DCGU_HW_MODULE_UART_1:
68*4882a593Smuzhiyun en1.bits.en_clkuart1 = enable;
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun case DCGU_HW_MODULE_PERI:
71*4882a593Smuzhiyun en1.bits.en_clkperi20 = enable;
72*4882a593Smuzhiyun break;
73*4882a593Smuzhiyun case DCGU_HW_MODULE_CPU:
74*4882a593Smuzhiyun en2.bits.en_clkcpu = enable;
75*4882a593Smuzhiyun break;
76*4882a593Smuzhiyun case DCGU_HW_MODULE_I2S:
77*4882a593Smuzhiyun en1.bits.en_clk_i2s_dly = enable;
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun case DCGU_HW_MODULE_ABP_SCC:
80*4882a593Smuzhiyun en1.bits.en_clk_scc_abp = enable;
81*4882a593Smuzhiyun break;
82*4882a593Smuzhiyun case DCGU_HW_MODULE_SPDIF:
83*4882a593Smuzhiyun en1.bits.en_clk_dtv_spdo = enable;
84*4882a593Smuzhiyun break;
85*4882a593Smuzhiyun case DCGU_HW_MODULE_AD:
86*4882a593Smuzhiyun en1.bits.en_clkad = enable;
87*4882a593Smuzhiyun break;
88*4882a593Smuzhiyun case DCGU_HW_MODULE_MVD:
89*4882a593Smuzhiyun en1.bits.en_clkmvd = enable;
90*4882a593Smuzhiyun break;
91*4882a593Smuzhiyun case DCGU_HW_MODULE_TSD:
92*4882a593Smuzhiyun en1.bits.en_clktsd = enable;
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun case DCGU_HW_MODULE_GA:
95*4882a593Smuzhiyun en1.bits.en_clkga = enable;
96*4882a593Smuzhiyun break;
97*4882a593Smuzhiyun case DCGU_HW_MODULE_DVP:
98*4882a593Smuzhiyun en1.bits.en_clkdvp = enable;
99*4882a593Smuzhiyun break;
100*4882a593Smuzhiyun case DCGU_HW_MODULE_MR2:
101*4882a593Smuzhiyun en1.bits.en_clkmr2 = enable;
102*4882a593Smuzhiyun break;
103*4882a593Smuzhiyun case DCGU_HW_MODULE_MR1:
104*4882a593Smuzhiyun en1.bits.en_clkmr1 = enable;
105*4882a593Smuzhiyun break;
106*4882a593Smuzhiyun default:
107*4882a593Smuzhiyun printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
108*4882a593Smuzhiyun __LINE__, module);
109*4882a593Smuzhiyun return -EINVAL;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun * The reg_read() following the reg_write() below forces the write to
114*4882a593Smuzhiyun * be really done on the bus.
115*4882a593Smuzhiyun * Otherwise the clock may not be switched on when this API function
116*4882a593Smuzhiyun * returns, which may cause an bus error if a registers of the hardware
117*4882a593Smuzhiyun * module connected to the clock is accessed.
118*4882a593Smuzhiyun */
119*4882a593Smuzhiyun if (module == DCGU_HW_MODULE_CPU) {
120*4882a593Smuzhiyun reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
121*4882a593Smuzhiyun en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
122*4882a593Smuzhiyun } else {
123*4882a593Smuzhiyun reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
124*4882a593Smuzhiyun en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
dcgu_set_reset_switch(enum dcgu_hw_module module,enum dcgu_switch setup)130*4882a593Smuzhiyun int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun union dcgu_reset_unit1 val;
133*4882a593Smuzhiyun u32 enable;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun switch (setup) {
136*4882a593Smuzhiyun case DCGU_SWITCH_ON:
137*4882a593Smuzhiyun enable = 1;
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun case DCGU_SWITCH_OFF:
140*4882a593Smuzhiyun enable = 0;
141*4882a593Smuzhiyun break;
142*4882a593Smuzhiyun default:
143*4882a593Smuzhiyun printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
144*4882a593Smuzhiyun setup);
145*4882a593Smuzhiyun return -EINVAL;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
149*4882a593Smuzhiyun switch (module) {
150*4882a593Smuzhiyun case DCGU_HW_MODULE_MSMC:
151*4882a593Smuzhiyun val.bits.swreset_clkmsmc = enable;
152*4882a593Smuzhiyun break;
153*4882a593Smuzhiyun case DCGU_HW_MODULE_SSI_S:
154*4882a593Smuzhiyun val.bits.swreset_clkssi_s = enable;
155*4882a593Smuzhiyun break;
156*4882a593Smuzhiyun case DCGU_HW_MODULE_SSI_M:
157*4882a593Smuzhiyun val.bits.swreset_clkssi_m = enable;
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun case DCGU_HW_MODULE_SMC:
160*4882a593Smuzhiyun val.bits.swreset_clksmc = enable;
161*4882a593Smuzhiyun break;
162*4882a593Smuzhiyun case DCGU_HW_MODULE_EBI:
163*4882a593Smuzhiyun val.bits.swreset_clkebi = enable;
164*4882a593Smuzhiyun break;
165*4882a593Smuzhiyun case DCGU_HW_MODULE_USB_60:
166*4882a593Smuzhiyun val.bits.swreset_clkusb60 = enable;
167*4882a593Smuzhiyun break;
168*4882a593Smuzhiyun case DCGU_HW_MODULE_USB_24:
169*4882a593Smuzhiyun val.bits.swreset_clkusb24 = enable;
170*4882a593Smuzhiyun break;
171*4882a593Smuzhiyun case DCGU_HW_MODULE_UART_2:
172*4882a593Smuzhiyun val.bits.swreset_clkuart2 = enable;
173*4882a593Smuzhiyun break;
174*4882a593Smuzhiyun case DCGU_HW_MODULE_UART_1:
175*4882a593Smuzhiyun val.bits.swreset_clkuart1 = enable;
176*4882a593Smuzhiyun break;
177*4882a593Smuzhiyun case DCGU_HW_MODULE_PWM:
178*4882a593Smuzhiyun val.bits.swreset_pwm = enable;
179*4882a593Smuzhiyun break;
180*4882a593Smuzhiyun case DCGU_HW_MODULE_GPT:
181*4882a593Smuzhiyun val.bits.swreset_gpt = enable;
182*4882a593Smuzhiyun break;
183*4882a593Smuzhiyun case DCGU_HW_MODULE_I2C2:
184*4882a593Smuzhiyun val.bits.swreset_i2c2 = enable;
185*4882a593Smuzhiyun break;
186*4882a593Smuzhiyun case DCGU_HW_MODULE_I2C1:
187*4882a593Smuzhiyun val.bits.swreset_i2c1 = enable;
188*4882a593Smuzhiyun break;
189*4882a593Smuzhiyun case DCGU_HW_MODULE_GPIO2:
190*4882a593Smuzhiyun val.bits.swreset_gpio2 = enable;
191*4882a593Smuzhiyun break;
192*4882a593Smuzhiyun case DCGU_HW_MODULE_GPIO1:
193*4882a593Smuzhiyun val.bits.swreset_gpio1 = enable;
194*4882a593Smuzhiyun break;
195*4882a593Smuzhiyun case DCGU_HW_MODULE_CPU:
196*4882a593Smuzhiyun val.bits.swreset_clkcpu = enable;
197*4882a593Smuzhiyun break;
198*4882a593Smuzhiyun case DCGU_HW_MODULE_I2S:
199*4882a593Smuzhiyun val.bits.swreset_clk_i2s_dly = enable;
200*4882a593Smuzhiyun break;
201*4882a593Smuzhiyun case DCGU_HW_MODULE_ABP_SCC:
202*4882a593Smuzhiyun val.bits.swreset_clk_scc_abp = enable;
203*4882a593Smuzhiyun break;
204*4882a593Smuzhiyun case DCGU_HW_MODULE_SPDIF:
205*4882a593Smuzhiyun val.bits.swreset_clk_dtv_spdo = enable;
206*4882a593Smuzhiyun break;
207*4882a593Smuzhiyun case DCGU_HW_MODULE_AD:
208*4882a593Smuzhiyun val.bits.swreset_clkad = enable;
209*4882a593Smuzhiyun break;
210*4882a593Smuzhiyun case DCGU_HW_MODULE_MVD:
211*4882a593Smuzhiyun val.bits.swreset_clkmvd = enable;
212*4882a593Smuzhiyun break;
213*4882a593Smuzhiyun case DCGU_HW_MODULE_TSD:
214*4882a593Smuzhiyun val.bits.swreset_clktsd = enable;
215*4882a593Smuzhiyun break;
216*4882a593Smuzhiyun case DCGU_HW_MODULE_TSIO:
217*4882a593Smuzhiyun val.bits.swreset_clktsio = enable;
218*4882a593Smuzhiyun break;
219*4882a593Smuzhiyun case DCGU_HW_MODULE_GA:
220*4882a593Smuzhiyun val.bits.swreset_clkga = enable;
221*4882a593Smuzhiyun break;
222*4882a593Smuzhiyun case DCGU_HW_MODULE_MPC:
223*4882a593Smuzhiyun val.bits.swreset_clkmpc = enable;
224*4882a593Smuzhiyun break;
225*4882a593Smuzhiyun case DCGU_HW_MODULE_CVE:
226*4882a593Smuzhiyun val.bits.swreset_clkcve = enable;
227*4882a593Smuzhiyun break;
228*4882a593Smuzhiyun case DCGU_HW_MODULE_DVP:
229*4882a593Smuzhiyun val.bits.swreset_clkdvp = enable;
230*4882a593Smuzhiyun break;
231*4882a593Smuzhiyun case DCGU_HW_MODULE_MR2:
232*4882a593Smuzhiyun val.bits.swreset_clkmr2 = enable;
233*4882a593Smuzhiyun break;
234*4882a593Smuzhiyun case DCGU_HW_MODULE_MR1:
235*4882a593Smuzhiyun val.bits.swreset_clkmr1 = enable;
236*4882a593Smuzhiyun break;
237*4882a593Smuzhiyun default:
238*4882a593Smuzhiyun printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
239*4882a593Smuzhiyun __LINE__, module);
240*4882a593Smuzhiyun return -EINVAL;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun return 0;
245*4882a593Smuzhiyun }
246