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Searched refs:pre_div (Results 1 – 25 of 50) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/pwm/
H A Dpwm-meson.c91 u8 pre_div; member
165 unsigned int duty, period, pre_div, cnt, duty_cnt; in meson_pwm_calc() local
182 pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL); in meson_pwm_calc()
183 if (pre_div > MISC_CLK_DIV_MASK) { in meson_pwm_calc()
188 cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1)); in meson_pwm_calc()
195 pre_div, cnt); in meson_pwm_calc()
198 channel->pre_div = pre_div; in meson_pwm_calc()
202 channel->pre_div = pre_div; in meson_pwm_calc()
208 NSEC_PER_SEC * (pre_div + 1)); in meson_pwm_calc()
215 duty, pre_div, duty_cnt); in meson_pwm_calc()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sun9i-cpus.c75 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
90 pre_div = div; in sun9i_a80_cpus_clk_round()
93 pre_div = DIV_ROUND_UP(div, 2); in sun9i_a80_cpus_clk_round()
96 pre_div = DIV_ROUND_UP(div, 3); in sun9i_a80_cpus_clk_round()
99 pre_div = DIV_ROUND_UP(div, 4); in sun9i_a80_cpus_clk_round()
107 *pre_divp = pre_div - 1; in sun9i_a80_cpus_clk_round()
110 return parent_rate / pre_div / div; in sun9i_a80_cpus_clk_round()
157 u8 div, pre_div, parent; in sun9i_a80_cpus_clk_set_rate() local
166 sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate); in sun9i_a80_cpus_clk_set_rate()
169 reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div); in sun9i_a80_cpus_clk_set_rate()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_ddc_clk.c18 u8 pre_div; member
29 const u8 pre_div, in sun4i_ddc_calc_divider() argument
40 tmp_rate = (((parent_rate / pre_div) / 10) >> _n) / in sun4i_ddc_calc_divider()
67 return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div, in sun4i_ddc_round_rate()
82 return (((parent_rate / ddc->pre_div) / 10) >> n) / in sun4i_ddc_recalc_rate()
92 sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div, in sun4i_ddc_set_rate()
134 ddc->pre_div = hdmi->variant->ddc_clk_pre_divider; in sun4i_ddc_create()
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dclk-rcg.c113 static u32 ns_to_pre_div(struct pre_div *p, u32 ns) in ns_to_pre_div()
120 static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns) in pre_div_to_ns() argument
128 ns |= pre_div << p->pre_div_shift; in pre_div_to_ns()
203 struct pre_div *p; in configure_bank()
267 ns = pre_div_to_ns(p, f->pre_div - 1, ns); in configure_bank()
312 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1; in clk_dyn_rcg_set_parent()
326 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div) in calc_rate() argument
328 if (pre_div) in calc_rate()
329 rate /= pre_div + 1; in calc_rate()
345 u32 pre_div, m = 0, n = 0, ns, md, mode = 0; in clk_rcg_recalc_rate() local
[all …]
H A Dclk-rcg2.c226 if (f->pre_div) { in _freq_tbl_determine_rate()
230 rate *= f->pre_div + 1; in _freq_tbl_determine_rate()
303 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; in __clk_rcg2_configure()
445 f.pre_div = hid_div; in clk_edp_pixel_set_rate()
446 f.pre_div >>= CFG_SRC_DIV_SHIFT; in clk_edp_pixel_set_rate()
447 f.pre_div &= mask; in clk_edp_pixel_set_rate()
553 f.pre_div = div; in clk_byte_set_rate()
612 f.pre_div = div; in clk_byte2_set_rate()
709 f.pre_div = hid_div; in clk_pixel_set_rate()
710 f.pre_div >>= CFG_SRC_DIV_SHIFT; in clk_pixel_set_rate()
[all …]
H A Dclk-rcg.h15 u8 pre_div; member
47 struct pre_div { struct
80 struct pre_div p;
118 struct pre_div p[2];
H A Dgcc-ipq4019.c1288 f->pre_div << pll->cdiv.shift); in clk_cpu_div_set_rate()
1309 u32 cdiv, pre_div; in clk_cpu_div_recalc_rate() local
1321 pre_div = (cdiv + 1) * 2; in clk_cpu_div_recalc_rate()
1323 pre_div = cdiv + 12; in clk_cpu_div_recalc_rate()
1326 do_div(rate, pre_div); in clk_cpu_div_recalc_rate()
1385 u32 cdiv, pre_div = 1; in clk_regmap_clk_div_recalc_rate() local
1390 pre_div = pll->fixed_div; in clk_regmap_clk_div_recalc_rate()
1397 pre_div = clkt->div; in clk_regmap_clk_div_recalc_rate()
1402 do_div(rate, pre_div); in clk_regmap_clk_div_recalc_rate()
/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-kona-setup.c72 div = &peri->pre_div; in clk_requires_trigger()
138 div = &peri->pre_div; in peri_clk_data_offsets_valid()
372 struct bcm_clk_div *pre_div; in kona_dividers_valid() local
377 if (!divider_exists(&peri->div) || !divider_exists(&peri->pre_div)) in kona_dividers_valid()
381 pre_div = &peri->pre_div; in kona_dividers_valid()
382 if (divider_is_fixed(div) || divider_is_fixed(pre_div)) in kona_dividers_valid()
387 return div->u.s.frac_width + pre_div->u.s.frac_width <= limit; in kona_dividers_valid()
408 struct bcm_clk_div *pre_div; in peri_clk_data_valid() local
450 pre_div = &peri->pre_div; in peri_clk_data_valid()
455 if (divider_exists(pre_div)) in peri_clk_data_valid()
[all …]
H A Dclk-kona.c694 struct bcm_clk_div *div, struct bcm_clk_div *pre_div, in clk_recalc_rate() argument
716 if (pre_div && divider_exists(pre_div)) { in clk_recalc_rate()
719 scaled_rate = scale_rate(pre_div, parent_rate); in clk_recalc_rate()
721 scaled_div = divider_read_scaled(ccu, pre_div); in clk_recalc_rate()
749 struct bcm_clk_div *pre_div, in round_rate() argument
774 if (divider_exists(pre_div)) { in round_rate()
778 scaled_rate = scale_rate(pre_div, parent_rate); in round_rate()
780 scaled_pre_div = divider_read_scaled(ccu, pre_div); in round_rate()
1004 return clk_recalc_rate(bcm_clk->ccu, &data->div, &data->pre_div, in kona_peri_clk_recalc_rate()
1018 return round_rate(bcm_clk->ccu, div, &bcm_clk->u.peri->pre_div, in kona_peri_clk_round_rate()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8173.c160 unsigned int pre_div; in mtk_hdmi_pll_set_rate() local
170 pre_div = 0; in mtk_hdmi_pll_set_rate()
173 pre_div = 1; in mtk_hdmi_pll_set_rate()
176 pre_div = 1; in mtk_hdmi_pll_set_rate()
181 (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV); in mtk_hdmi_pll_set_rate()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx7/
H A Dclock_slice.h101 int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div);
102 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
111 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-sparx5.c53 u8 pre_div; member
65 int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div); in s5_calc_freq()
91 conf->pre_div = i; in s5_search_fractional()
183 val |= FIELD_PREP(PLL_PRE_DIV, conf.pre_div); in s5_pll_set_rate()
203 conf.pre_div = FIELD_GET(PLL_PRE_DIV, val); in s5_pll_recalc_rate()
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx7/
H A Dclock_slice.c458 int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div) in clock_set_prediv() argument
476 if (pre_div != CLK_ROOT_PRE_DIV1) { in clock_set_prediv()
484 reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT; in clock_set_prediv()
490 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div) in clock_get_prediv() argument
508 *pre_div = 0; in clock_get_prediv()
516 *pre_div = val; in clock_get_prediv()
672 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, in clock_root_cfg() argument
691 if (pre_div != CLK_ROOT_PRE_DIV1) { in clock_root_cfg()
716 val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT | in clock_root_cfg()
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/
H A Dcpu.c57 int pre_div; in clk_get() local
79 pre_div = (readl(pll_base + PLLC_PREDIV) & in clk_get()
83 pll_out /= pre_div; in clk_get()
/OK3568_Linux_fs/u-boot/drivers/spi/
H A Dmxc_spi.c136 u32 pre_div = 0, post_div = 0; in spi_cfg_mxc() local
152 pre_div = (clk_src - 1) / max_hz; in spi_cfg_mxc()
154 post_div = fls(pre_div); in spi_cfg_mxc()
162 pre_div >>= post_div; in spi_cfg_mxc()
168 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); in spi_cfg_mxc()
172 MXC_CSPICTRL_PREDIV(pre_div); in spi_cfg_mxc()
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Drt1016.c310 int pre_div, bclk_ms, frame_size; in rt1016_hw_params() local
314 pre_div = rl6231_get_clk_info(rt1016->sysclk, rt1016->lrck); in rt1016_hw_params()
315 if (pre_div < 0) { in rt1016_hw_params()
335 rt1016->lrck, pre_div, dai->id); in rt1016_hw_params()
358 ((pre_div + 3) << RT1016_FS_PD_SFT) | in rt1016_hw_params()
359 (pre_div << RT1016_OSR_PD_SFT)); in rt1016_hw_params()
H A Drt1308.c459 int pre_div, bclk_ms, frame_size; in rt1308_hw_params() local
462 pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck); in rt1308_hw_params()
463 if (pre_div < 0) { in rt1308_hw_params()
480 bclk_ms, pre_div, dai->id); in rt1308_hw_params()
483 rt1308->lrck, pre_div, dai->id); in rt1308_hw_params()
505 val_clk = pre_div << RT1308_DIV_FS_SYS_SFT; in rt1308_hw_params()
H A Drt1015.c729 int pre_div, bclk_ms, frame_size; in rt1015_hw_params() local
733 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck); in rt1015_hw_params()
734 if (pre_div < 0) { in rt1015_hw_params()
750 bclk_ms, pre_div, dai->id); in rt1015_hw_params()
753 rt1015->lrck, pre_div, dai->id); in rt1015_hw_params()
774 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT); in rt1015_hw_params()
H A Drt1305.c631 int pre_div, bclk_ms, frame_size; in rt1305_hw_params() local
634 pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck); in rt1305_hw_params()
635 if (pre_div < 0) { in rt1305_hw_params()
641 pre_div = 0; in rt1305_hw_params()
654 bclk_ms, pre_div, dai->id); in rt1305_hw_params()
657 rt1305->lrck, pre_div, dai->id); in rt1305_hw_params()
679 val_clk = pre_div << RT1305_DIV_FS_SYS_SFT; in rt1305_hw_params()
H A Dwm8510.c266 unsigned int pre_div:4; /* prescale - 1 */ member
285 pll_div.pre_div = 1; in pll_factors()
288 pll_div.pre_div = 0; in pll_factors()
332 snd_soc_component_write(component, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n); in wm8510_set_dai_pll()
H A Drt5514.c756 int pre_div, bclk_ms, frame_size; in rt5514_hw_params() local
760 pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck); in rt5514_hw_params()
761 if (pre_div < 0) { in rt5514_hw_params()
778 bclk_ms, pre_div, dai->id); in rt5514_hw_params()
800 (pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT); in rt5514_hw_params()
803 pre_div << RT5514_CLK_SYS_DIV_OUT_SFT | in rt5514_hw_params()
804 pre_div << RT5514_SEL_ADC_OSR_SFT); in rt5514_hw_params()
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-of-esdhc.c648 unsigned int pre_div = 1, div = 1; in esdhc_of_set_clock() local
661 pre_div = 2; in esdhc_of_set_clock()
674 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256) in esdhc_of_set_clock()
675 pre_div *= 2; in esdhc_of_set_clock()
677 while (host->max_clk / pre_div / div > clock_fixup && div < 16) in esdhc_of_set_clock()
680 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
688 pre_div = 4; in esdhc_of_set_clock()
691 pre_div = 4; in esdhc_of_set_clock()
694 pre_div = 4; in esdhc_of_set_clock()
700 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
[all …]
/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-ac100.c226 int div = 0, pre_div = 0; in ac100_clkout_set_rate() local
229 div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div, in ac100_clkout_set_rate()
235 ac100_clkout_prediv[++pre_div].div); in ac100_clkout_set_rate()
240 pre_div = ac100_clkout_prediv[pre_div].val; in ac100_clkout_set_rate()
246 (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT); in ac100_clkout_set_rate()
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c474 u32 reg, pre_div, infreq, mult; in decode_pll() local
490 pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> in decode_pll()
492 pre_div += 1; in decode_pll()
507 infreq = infreq / pre_div; in decode_pll()
519 pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> in decode_pll()
521 pre_div += 1; in decode_pll()
536 infreq = infreq / pre_div; in decode_pll()
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dfsl_esdhc.c533 int pre_div = 1; in set_sysctl() local
535 int pre_div = 2; in set_sysctl() local
545 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) in set_sysctl()
546 pre_div *= 2; in set_sysctl()
548 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) in set_sysctl()
551 pre_div >>= mmc_card_ddr(mmc) ? 2 : 1; in set_sysctl()
554 clk = (pre_div << 8) | (div << 4); in set_sysctl()

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