1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: 5*4882a593Smuzhiyun * Peng Fan <Peng.Fan@freescale.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ASM_ARCH_CLOCK_SLICE_H 11*4882a593Smuzhiyun #define _ASM_ARCH_CLOCK_SLICE_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun enum root_pre_div { 14*4882a593Smuzhiyun CLK_ROOT_PRE_DIV1 = 0, 15*4882a593Smuzhiyun CLK_ROOT_PRE_DIV2, 16*4882a593Smuzhiyun CLK_ROOT_PRE_DIV3, 17*4882a593Smuzhiyun CLK_ROOT_PRE_DIV4, 18*4882a593Smuzhiyun CLK_ROOT_PRE_DIV5, 19*4882a593Smuzhiyun CLK_ROOT_PRE_DIV6, 20*4882a593Smuzhiyun CLK_ROOT_PRE_DIV7, 21*4882a593Smuzhiyun CLK_ROOT_PRE_DIV8, 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun enum root_post_div { 25*4882a593Smuzhiyun CLK_ROOT_POST_DIV1 = 0, 26*4882a593Smuzhiyun CLK_ROOT_POST_DIV2, 27*4882a593Smuzhiyun CLK_ROOT_POST_DIV3, 28*4882a593Smuzhiyun CLK_ROOT_POST_DIV4, 29*4882a593Smuzhiyun CLK_ROOT_POST_DIV5, 30*4882a593Smuzhiyun CLK_ROOT_POST_DIV6, 31*4882a593Smuzhiyun CLK_ROOT_POST_DIV7, 32*4882a593Smuzhiyun CLK_ROOT_POST_DIV8, 33*4882a593Smuzhiyun CLK_ROOT_POST_DIV9, 34*4882a593Smuzhiyun CLK_ROOT_POST_DIV10, 35*4882a593Smuzhiyun CLK_ROOT_POST_DIV11, 36*4882a593Smuzhiyun CLK_ROOT_POST_DIV12, 37*4882a593Smuzhiyun CLK_ROOT_POST_DIV13, 38*4882a593Smuzhiyun CLK_ROOT_POST_DIV14, 39*4882a593Smuzhiyun CLK_ROOT_POST_DIV15, 40*4882a593Smuzhiyun CLK_ROOT_POST_DIV16, 41*4882a593Smuzhiyun CLK_ROOT_POST_DIV17, 42*4882a593Smuzhiyun CLK_ROOT_POST_DIV18, 43*4882a593Smuzhiyun CLK_ROOT_POST_DIV19, 44*4882a593Smuzhiyun CLK_ROOT_POST_DIV20, 45*4882a593Smuzhiyun CLK_ROOT_POST_DIV21, 46*4882a593Smuzhiyun CLK_ROOT_POST_DIV22, 47*4882a593Smuzhiyun CLK_ROOT_POST_DIV23, 48*4882a593Smuzhiyun CLK_ROOT_POST_DIV24, 49*4882a593Smuzhiyun CLK_ROOT_POST_DIV25, 50*4882a593Smuzhiyun CLK_ROOT_POST_DIV26, 51*4882a593Smuzhiyun CLK_ROOT_POST_DIV27, 52*4882a593Smuzhiyun CLK_ROOT_POST_DIV28, 53*4882a593Smuzhiyun CLK_ROOT_POST_DIV29, 54*4882a593Smuzhiyun CLK_ROOT_POST_DIV30, 55*4882a593Smuzhiyun CLK_ROOT_POST_DIV31, 56*4882a593Smuzhiyun CLK_ROOT_POST_DIV32, 57*4882a593Smuzhiyun CLK_ROOT_POST_DIV33, 58*4882a593Smuzhiyun CLK_ROOT_POST_DIV34, 59*4882a593Smuzhiyun CLK_ROOT_POST_DIV35, 60*4882a593Smuzhiyun CLK_ROOT_POST_DIV36, 61*4882a593Smuzhiyun CLK_ROOT_POST_DIV37, 62*4882a593Smuzhiyun CLK_ROOT_POST_DIV38, 63*4882a593Smuzhiyun CLK_ROOT_POST_DIV39, 64*4882a593Smuzhiyun CLK_ROOT_POST_DIV40, 65*4882a593Smuzhiyun CLK_ROOT_POST_DIV41, 66*4882a593Smuzhiyun CLK_ROOT_POST_DIV42, 67*4882a593Smuzhiyun CLK_ROOT_POST_DIV43, 68*4882a593Smuzhiyun CLK_ROOT_POST_DIV44, 69*4882a593Smuzhiyun CLK_ROOT_POST_DIV45, 70*4882a593Smuzhiyun CLK_ROOT_POST_DIV46, 71*4882a593Smuzhiyun CLK_ROOT_POST_DIV47, 72*4882a593Smuzhiyun CLK_ROOT_POST_DIV48, 73*4882a593Smuzhiyun CLK_ROOT_POST_DIV49, 74*4882a593Smuzhiyun CLK_ROOT_POST_DIV50, 75*4882a593Smuzhiyun CLK_ROOT_POST_DIV51, 76*4882a593Smuzhiyun CLK_ROOT_POST_DIV52, 77*4882a593Smuzhiyun CLK_ROOT_POST_DIV53, 78*4882a593Smuzhiyun CLK_ROOT_POST_DIV54, 79*4882a593Smuzhiyun CLK_ROOT_POST_DIV55, 80*4882a593Smuzhiyun CLK_ROOT_POST_DIV56, 81*4882a593Smuzhiyun CLK_ROOT_POST_DIV57, 82*4882a593Smuzhiyun CLK_ROOT_POST_DIV58, 83*4882a593Smuzhiyun CLK_ROOT_POST_DIV59, 84*4882a593Smuzhiyun CLK_ROOT_POST_DIV60, 85*4882a593Smuzhiyun CLK_ROOT_POST_DIV61, 86*4882a593Smuzhiyun CLK_ROOT_POST_DIV62, 87*4882a593Smuzhiyun CLK_ROOT_POST_DIV63, 88*4882a593Smuzhiyun CLK_ROOT_POST_DIV64, 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun enum root_auto_div { 92*4882a593Smuzhiyun CLK_ROOT_AUTO_DIV1 = 0, 93*4882a593Smuzhiyun CLK_ROOT_AUTO_DIV2, 94*4882a593Smuzhiyun CLK_ROOT_AUTO_DIV4, 95*4882a593Smuzhiyun CLK_ROOT_AUTO_DIV8, 96*4882a593Smuzhiyun CLK_ROOT_AUTO_DIV16, 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src); 100*4882a593Smuzhiyun int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); 101*4882a593Smuzhiyun int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div); 102*4882a593Smuzhiyun int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); 103*4882a593Smuzhiyun int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div); 104*4882a593Smuzhiyun int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div); 105*4882a593Smuzhiyun int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div, 106*4882a593Smuzhiyun int auto_en); 107*4882a593Smuzhiyun int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div, 108*4882a593Smuzhiyun int *auto_en); 109*4882a593Smuzhiyun int clock_get_target_val(enum clk_root_index clock_id, u32 *val); 110*4882a593Smuzhiyun int clock_set_target_val(enum clk_root_index clock_id, u32 val); 111*4882a593Smuzhiyun int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, 112*4882a593Smuzhiyun enum root_post_div post_div, enum clk_root_src clock_src); 113*4882a593Smuzhiyun int clock_root_enabled(enum clk_root_index clock_id); 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun int clock_enable(enum clk_ccgr_index index, bool enable); 116*4882a593Smuzhiyun #endif 117