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Searched refs:input_rate (Results 1 – 25 of 32) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-pll.c24 unsigned long input_rate; member
73 rate = pll->input_rate; in mmp_clk_pll_recalc_rate()
104 unsigned long input_rate, in mmp_clk_register_pll() argument
127 pll->input_rate = input_rate; in mmp_clk_register_pll()
159 clks[i].input_rate, in mmp_register_pll_clks()
H A Dclk.h235 unsigned long input_rate; member
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-pll.c526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
527 if (sel->input_rate == parent_rate && in _get_table_rate()
531 if (sel->input_rate == 0) in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
956 unsigned long input_rate; in clk_plle_enable() local
963 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in clk_plle_enable()
965 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
1119 unsigned long flags = 0, input_rate; in clk_pllu_enable() local
1129 input_rate = clk_hw_get_rate(osc); in clk_pllu_enable()
1142 if (input_rate == utmi_parameters[i].osc_frequency) { in clk_pllu_enable()
[all …]
H A Dclk-tegra210.c1060 unsigned long input_rate; in pllx_get_dyn_steps() local
1064 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in pllx_get_dyn_steps()
1066 input_rate = 38400000; in pllx_get_dyn_steps()
1068 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); in pllx_get_dyn_steps()
1070 switch (input_rate) { in pllx_get_dyn_steps()
1087 __func__, input_rate); in pllx_get_dyn_steps()
1413 cfg->input_rate / cfg->m * cfg->n / in tegra210_pllx_dyn_ramp()
1429 unsigned long rate, unsigned long input_rate) in tegra210_pll_fixed_mdiv_cfg() argument
1450 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); in tegra210_pll_fixed_mdiv_cfg()
1459 cf = input_rate / cfg->m; in tegra210_pll_fixed_mdiv_cfg()
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H A Dclk.h165 unsigned long input_rate; member
905 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
/OK3568_Linux_fs/u-boot/drivers/spi/
H A Drk_spi.c54 uint input_rate; member
95 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk()
107 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
301 priv->input_rate = ret; in rockchip_spi_probe()
302 debug("%s: rate = %u\n", __func__, priv->input_rate); in rockchip_spi_probe()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h193 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) in clk_get_divisor() argument
197 clk_div = input_rate / output_rate; in clk_get_divisor()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3066.c90 #define RATE_TO_DIV(input_rate, output_rate) \ argument
91 ((input_rate) / (output_rate) - 1);
93 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3036.c44 #define RATE_TO_DIV(input_rate, output_rate) \ argument
45 ((input_rate) / (output_rate) - 1);
47 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3328.c23 #define RATE_TO_DIV(input_rate, output_rate) \ argument
24 ((input_rate) / (output_rate) - 1);
25 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3188.c91 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3399.c44 #define RATE_TO_DIV(input_rate, output_rate) \ argument
45 ((input_rate) / (output_rate) - 1);
46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rv1108.c29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3128.c23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk322x.c22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3308.c29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3288.c210 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk1808.c30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rv1106.c23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dclock.c1396 unsigned int fine_scalar_bits, unsigned int input_rate, in clock_calc_best_scalar() argument
1405 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, in clock_calc_best_scalar()
1413 if (input_rate == 0 || target_rate == 0) in clock_calc_best_scalar()
1416 if (target_rate >= input_rate) in clock_calc_best_scalar()
1421 max(min(input_rate / i / target_rate, cap), 1U); in clock_calc_best_scalar()
1422 const unsigned int effective_rate = input_rate / i / in clock_calc_best_scalar()
/OK3568_Linux_fs/kernel/sound/pci/ctxfi/
H A Dctatc.c195 atc_get_pitch(unsigned int input_rate, unsigned int output_rate) in atc_get_pitch() argument
201 pitch = (input_rate / output_rate) << 24; in atc_get_pitch()
202 input_rate %= output_rate; in atc_get_pitch()
203 input_rate /= 100; in atc_get_pitch()
205 for (b = 31; ((b >= 0) && !(input_rate >> b)); ) in atc_get_pitch()
209 input_rate <<= (31 - b); in atc_get_pitch()
210 input_rate /= output_rate; in atc_get_pitch()
213 input_rate <<= b; in atc_get_pitch()
215 input_rate >>= -b; in atc_get_pitch()
217 pitch |= input_rate; in atc_get_pitch()
/OK3568_Linux_fs/u-boot/drivers/clk/aspeed/
H A Dclk_ast2500.c179 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2500_calc_clock_config() argument
186 const ulong input_rate_khz = input_rate / 1000; in ast2500_calc_clock_config()
/OK3568_Linux_fs/kernel/arch/c6x/platforms/
H A Dpll.c224 rate = pll->input_rate; in clk_sysclk_recalc()
276 rate = pll->input_rate = clk->parent->rate; in clk_pllclk_recalc()
/OK3568_Linux_fs/kernel/arch/c6x/include/asm/
H A Dclock.h109 u32 input_rate; member
/OK3568_Linux_fs/kernel/sound/soc/stm/
H A Dstm32_sai_sub.c315 unsigned long input_rate, in stm32_sai_get_clk_div() argument
321 div = DIV_ROUND_CLOSEST(input_rate, output_rate); in stm32_sai_get_clk_div()
328 if (input_rate % div) in stm32_sai_get_clk_div()
331 output_rate, input_rate / div); in stm32_sai_get_clk_div()

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