1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * TI C64X clock definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010, 2011 Texas Instruments. 6*4882a593Smuzhiyun * Contributed by: Mark Salter <msalter@redhat.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copied heavily from arm/mach-davinci/clock.h, so: 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright (C) 2006-2007 Texas Instruments. 11*4882a593Smuzhiyun * Copyright (C) 2008-2009 Deep Root Systems, LLC 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _ASM_C6X_CLOCK_H 15*4882a593Smuzhiyun #define _ASM_C6X_CLOCK_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __ASSEMBLER__ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include <linux/list.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* PLL/Reset register offsets */ 22*4882a593Smuzhiyun #define PLLCTL 0x100 23*4882a593Smuzhiyun #define PLLM 0x110 24*4882a593Smuzhiyun #define PLLPRE 0x114 25*4882a593Smuzhiyun #define PLLDIV1 0x118 26*4882a593Smuzhiyun #define PLLDIV2 0x11c 27*4882a593Smuzhiyun #define PLLDIV3 0x120 28*4882a593Smuzhiyun #define PLLPOST 0x128 29*4882a593Smuzhiyun #define PLLCMD 0x138 30*4882a593Smuzhiyun #define PLLSTAT 0x13c 31*4882a593Smuzhiyun #define PLLALNCTL 0x140 32*4882a593Smuzhiyun #define PLLDCHANGE 0x144 33*4882a593Smuzhiyun #define PLLCKEN 0x148 34*4882a593Smuzhiyun #define PLLCKSTAT 0x14c 35*4882a593Smuzhiyun #define PLLSYSTAT 0x150 36*4882a593Smuzhiyun #define PLLDIV4 0x160 37*4882a593Smuzhiyun #define PLLDIV5 0x164 38*4882a593Smuzhiyun #define PLLDIV6 0x168 39*4882a593Smuzhiyun #define PLLDIV7 0x16c 40*4882a593Smuzhiyun #define PLLDIV8 0x170 41*4882a593Smuzhiyun #define PLLDIV9 0x174 42*4882a593Smuzhiyun #define PLLDIV10 0x178 43*4882a593Smuzhiyun #define PLLDIV11 0x17c 44*4882a593Smuzhiyun #define PLLDIV12 0x180 45*4882a593Smuzhiyun #define PLLDIV13 0x184 46*4882a593Smuzhiyun #define PLLDIV14 0x188 47*4882a593Smuzhiyun #define PLLDIV15 0x18c 48*4882a593Smuzhiyun #define PLLDIV16 0x190 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* PLLM register bits */ 51*4882a593Smuzhiyun #define PLLM_PLLM_MASK 0xff 52*4882a593Smuzhiyun #define PLLM_VAL(x) ((x) - 1) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* PREDIV register bits */ 55*4882a593Smuzhiyun #define PLLPREDIV_EN BIT(15) 56*4882a593Smuzhiyun #define PLLPREDIV_VAL(x) ((x) - 1) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* PLLCTL register bits */ 59*4882a593Smuzhiyun #define PLLCTL_PLLEN BIT(0) 60*4882a593Smuzhiyun #define PLLCTL_PLLPWRDN BIT(1) 61*4882a593Smuzhiyun #define PLLCTL_PLLRST BIT(3) 62*4882a593Smuzhiyun #define PLLCTL_PLLDIS BIT(4) 63*4882a593Smuzhiyun #define PLLCTL_PLLENSRC BIT(5) 64*4882a593Smuzhiyun #define PLLCTL_CLKMODE BIT(8) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* PLLCMD register bits */ 67*4882a593Smuzhiyun #define PLLCMD_GOSTAT BIT(0) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* PLLSTAT register bits */ 70*4882a593Smuzhiyun #define PLLSTAT_GOSTAT BIT(0) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* PLLDIV register bits */ 73*4882a593Smuzhiyun #define PLLDIV_EN BIT(15) 74*4882a593Smuzhiyun #define PLLDIV_RATIO_MASK 0x1f 75*4882a593Smuzhiyun #define PLLDIV_RATIO(x) ((x) - 1) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct pll_data; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct clk { 80*4882a593Smuzhiyun struct list_head node; 81*4882a593Smuzhiyun struct module *owner; 82*4882a593Smuzhiyun const char *name; 83*4882a593Smuzhiyun unsigned long rate; 84*4882a593Smuzhiyun int usecount; 85*4882a593Smuzhiyun u32 flags; 86*4882a593Smuzhiyun struct clk *parent; 87*4882a593Smuzhiyun struct list_head children; /* list of children */ 88*4882a593Smuzhiyun struct list_head childnode; /* parent's child list node */ 89*4882a593Smuzhiyun struct pll_data *pll_data; 90*4882a593Smuzhiyun u32 div; 91*4882a593Smuzhiyun unsigned long (*recalc) (struct clk *); 92*4882a593Smuzhiyun int (*set_rate) (struct clk *clk, unsigned long rate); 93*4882a593Smuzhiyun int (*round_rate) (struct clk *clk, unsigned long rate); 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Clock flags: SoC-specific flags start at BIT(16) */ 97*4882a593Smuzhiyun #define ALWAYS_ENABLED BIT(1) 98*4882a593Smuzhiyun #define CLK_PLL BIT(2) /* PLL-derived clock */ 99*4882a593Smuzhiyun #define PRE_PLL BIT(3) /* source is before PLL mult/div */ 100*4882a593Smuzhiyun #define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */ 101*4882a593Smuzhiyun #define FIXED_RATE_PLL BIT(5) /* fixed output rate PLL */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define MAX_PLL_SYSCLKS 16 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun struct pll_data { 106*4882a593Smuzhiyun void __iomem *base; 107*4882a593Smuzhiyun u32 num; 108*4882a593Smuzhiyun u32 flags; 109*4882a593Smuzhiyun u32 input_rate; 110*4882a593Smuzhiyun u32 bypass_delay; /* in loops */ 111*4882a593Smuzhiyun u32 reset_delay; /* in loops */ 112*4882a593Smuzhiyun u32 lock_delay; /* in loops */ 113*4882a593Smuzhiyun struct clk sysclks[MAX_PLL_SYSCLKS + 1]; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* pll_data flag bit */ 117*4882a593Smuzhiyun #define PLL_HAS_PRE BIT(0) 118*4882a593Smuzhiyun #define PLL_HAS_MUL BIT(1) 119*4882a593Smuzhiyun #define PLL_HAS_POST BIT(2) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define CLK(dev, con, ck) \ 122*4882a593Smuzhiyun { \ 123*4882a593Smuzhiyun .dev_id = dev, \ 124*4882a593Smuzhiyun .con_id = con, \ 125*4882a593Smuzhiyun .clk = ck, \ 126*4882a593Smuzhiyun } \ 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun extern void c6x_clks_init(struct clk_lookup *clocks); 129*4882a593Smuzhiyun extern int clk_register(struct clk *clk); 130*4882a593Smuzhiyun extern void clk_unregister(struct clk *clk); 131*4882a593Smuzhiyun extern void c64x_setup_clocks(void); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun extern struct pll_data c6x_soc_pll1; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun extern struct clk clkin1; 136*4882a593Smuzhiyun extern struct clk c6x_core_clk; 137*4882a593Smuzhiyun extern struct clk c6x_i2c_clk; 138*4882a593Smuzhiyun extern struct clk c6x_watchdog_clk; 139*4882a593Smuzhiyun extern struct clk c6x_mcbsp1_clk; 140*4882a593Smuzhiyun extern struct clk c6x_mcbsp2_clk; 141*4882a593Smuzhiyun extern struct clk c6x_mdio_clk; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #endif /* _ASM_C6X_CLOCK_H */ 146