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Searched refs:ep0state (Results 1 – 25 of 30) sorted by relevance

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/OK3568_Linux_fs/u-boot/drivers/usb/gadget/
H A Dpxa27x_udc.c27 static int ep0state = EP0_IDLE; variable
128 ep0state = EP0_IDLE; in udc_write_urb()
130 ep0state = EP0_XFER_COMPLETE; in udc_write_urb()
215 ep0state = EP0_IDLE; in udc_handle_ep0()
219 if ((udccsr0 & UDCCSR0_SA) != 0 && ep0state != EP0_IDLE) in udc_handle_ep0()
220 ep0state = EP0_IDLE; in udc_handle_ep0()
222 switch (ep0state) { in udc_handle_ep0()
259 ep0state = EP0_IDLE; in udc_handle_ep0()
265 ep0state = EP0_OUT_DATA; in udc_handle_ep0()
284 ep0state = EP0_IDLE; in udc_handle_ep0()
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H A Ddwc2_udc_otg_xfer_dma.c41 dev->ep0state = WAIT_FOR_IN_COMPLETE; in dwc2_udc_ep0_zlp()
245 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) { in complete_rx()
249 dev->ep0state = WAIT_FOR_IN_COMPLETE; in complete_rx()
273 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) { in complete_tx()
274 dev->ep0state = WAIT_FOR_OUT_COMPLETE; in complete_tx()
302 if (dev->ep0state == DATA_STATE_XMIT) { in complete_tx()
309 dev->ep0state = WAIT_FOR_COMPLETE; in complete_tx()
310 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) { in complete_tx()
315 dev->ep0state = WAIT_FOR_SETUP; in complete_tx()
316 } else if (dev->ep0state == WAIT_FOR_COMPLETE) { in complete_tx()
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H A Dpxa25x_udc.c103 if (dev->ep0state == EP0_STALL in udc_watchdog()
143 label, state_name[the_controller->ep0state], udccs0, in dump_udccs0()
161 state_name[dev->ep0state], in dump_state()
441 dev->ep0state = EP0_IDLE; in ep0_idle()
773 switch (dev->ep0state) { in pxa25x_ep_queue()
791 dev->ep0state = EP0_END_XFER; in pxa25x_ep_queue()
810 dev->ep0state); in pxa25x_ep_queue()
926 ep->dev->ep0state = EP0_STALL; in pxa25x_ep_set_halt()
1135 dev->ep0state = EP0_IDLE; in udc_reinit()
1239 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { in handle_ep0()
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H A Ddwc2_udc_otg_priv.h81 int ep0state; member
H A Dpxa25x_udc.h122 enum ep0_state ep0state; member
H A Ddwc2_udc_otg.c175 dev->ep0state = WAIT_FOR_SETUP; in udc_disable()
195 dev->ep0state = WAIT_FOR_SETUP; in udc_reinit()
/OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/
H A Dbcm63xx_udc.c317 int ep0state; member
974 udc->ep0state = EP0_SHUTDOWN; in bcm63xx_init_udc_hw()
1541 udc->ep0state = EP0_IN_FAKE_STATUS_PHASE; in bcm63xx_ep0_do_idle()
1545 udc->ep0state = EP0_IN_FAKE_STATUS_PHASE; in bcm63xx_ep0_do_idle()
1547 udc->ep0state = bcm63xx_ep0_do_setup(udc); in bcm63xx_ep0_do_idle()
1548 return udc->ep0state == EP0_IDLE ? -EAGAIN : 0; in bcm63xx_ep0_do_idle()
1559 udc->ep0state = EP0_SHUTDOWN; in bcm63xx_ep0_do_idle()
1583 enum bcm63xx_ep0_state ep0state = udc->ep0state; in bcm63xx_ep0_one_round() local
1586 switch (udc->ep0state) { in bcm63xx_ep0_one_round()
1591 ep0state = EP0_IDLE; in bcm63xx_ep0_one_round()
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H A Dgoku_udc.c254 if (dev->ep0state == EP0_SUSPEND) in goku_ep_disable()
362 if (unlikely(ep->num == 0 && dev->ep0state != EP0_IN)) in write_fifo()
380 dev->ep0state = EP0_STATUS; in write_fifo()
420 if (unlikely(ep->num == 0 && ep->dev->ep0state != EP0_OUT)) in read_fifo()
486 ep->dev->ep0state = EP0_STATUS; in read_fifo()
732 if (dev->ep0state == EP0_SUSPEND) in goku_queue()
825 if (dev->ep0state == EP0_SUSPEND) in goku_dequeue()
893 ep->dev->ep0state = EP0_STALL; in goku_set_halt()
1089 static const char *udc_ep_state(enum ep0state state) in udc_ep_state()
1160 udc_ep_state(dev->ep0state)); in udc_proc_read()
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H A Ds3c2410_udc.c350 ep->dev->ep0state = EP0_IDLE; in s3c2410_udc_write_fifo()
474 ep->dev->ep0state = EP0_IDLE; in s3c2410_udc_read_fifo()
679 dev->ep0state = EP0_IN_DATA_PHASE; in s3c2410_udc_handle_ep0_idle()
681 dev->ep0state = EP0_OUT_DATA_PHASE; in s3c2410_udc_handle_ep0_idle()
704 dev->ep0state = EP0_IDLE; in s3c2410_udc_handle_ep0_idle()
711 dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]); in s3c2410_udc_handle_ep0_idle()
733 ep0csr, ep0states[dev->ep0state]); in s3c2410_udc_handle_ep0()
740 dev->ep0state = EP0_IDLE; in s3c2410_udc_handle_ep0()
749 dev->ep0state = EP0_IDLE; in s3c2410_udc_handle_ep0()
752 switch (dev->ep0state) { in s3c2410_udc_handle_ep0()
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H A Ds3c-hsudc.c149 int ep0state; member
203 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_complete_request()
587 hsudc->ep0state = DATA_STATE_XMIT; in s3c_hsudc_process_setup()
590 hsudc->ep0state = DATA_STATE_RECV; in s3c_hsudc_process_setup()
597 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_process_setup()
611 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_process_setup()
622 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_process_setup()
629 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_process_setup()
658 hsudc->ep0state = WAIT_FOR_SETUP; in s3c_hsudc_handle_ep0_intr()
676 if (hsudc->ep0state == WAIT_FOR_SETUP) in s3c_hsudc_handle_ep0_intr()
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H A Dpxa25x_udc.h98 enum ep0_state ep0state; member
185 label, state_name[the_controller->ep0state], udccs0, in dump_udccs0()
205 state_name[dev->ep0state], in dump_state()
H A Dgr_udc.c194 seq_printf(seq, "ep0state = %s\n", gr_ep0state_string(dev->ep0state)); in gr_dfs_show()
599 if (dev->ep0state == GR_EP0_SUSPEND) { in gr_queue()
695 dev->ep0state = GR_EP0_STALL; in gr_control_stall()
751 if (dev->ep0state != value) in gr_set_ep0state()
754 dev->ep0state = value; in gr_set_ep0state()
1059 if (dev->ep0state == GR_EP0_STALL) { in gr_ep0_setup()
1065 if (dev->ep0state == GR_EP0_ISTATUS) { in gr_ep0_setup()
1073 } else if (dev->ep0state != GR_EP0_SETUP) { in gr_ep0_setup()
1076 gr_ep0state_string(dev->ep0state)); in gr_ep0_setup()
1082 gr_ep0state_string(dev->ep0state)); in gr_ep0_setup()
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H A Dgoku_udc.h229 enum ep0state { enum
245 enum ep0state ep0state; member
H A Dpxa25x_udc.c567 dev->ep0state = EP0_IDLE; in ep0_idle()
887 switch (dev->ep0state) { in pxa25x_ep_queue()
904 dev->ep0state = EP0_END_XFER; in pxa25x_ep_queue()
919 DMSG("ep0 i/o, odd state %d\n", dev->ep0state); in pxa25x_ep_queue()
1034 ep->dev->ep0state = EP0_STALL; in pxa25x_ep_set_halt()
1386 dev->ep0state = EP0_IDLE; in udc_reinit()
1618 if (dev->ep0state == EP0_STALL in udc_watchdog()
1653 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { in handle_ep0()
1659 switch (dev->ep0state) { in handle_ep0()
1735 dev->ep0state = EP0_IN_DATA_PHASE; in handle_ep0()
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H A Dlpc32xx_udc.c167 int ep0state; member
1394 udc->ep0state = WAIT_FOR_SETUP; in udc_reinit()
1473 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_in_req()
1495 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_out_req()
1513 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_out_req()
1807 udc->ep0state = DATA_IN; in lpc32xx_ep_queue()
1811 udc->ep0state = DATA_OUT; in lpc32xx_ep_queue()
2302 udc->ep0state = WAIT_FOR_SETUP; in udc_handle_ep0_setup()
2338 udc->ep0state = WAIT_FOR_SETUP; in udc_handle_ep0_in()
2345 if (udc->ep0state == DATA_IN) in udc_handle_ep0_in()
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H A Ds3c2410_udc.h84 int ep0state; member
H A Dpxa27x_udc.h404 #define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
460 enum ep0_state ep0state; member
H A Dgr_udc.h195 enum gr_ep0state ep0state; member
/OK3568_Linux_fs/kernel/drivers/usb/dwc3/
H A Ddebug.h256 const struct dwc3_event_depevt *event, u32 ep0state) in dwc3_ep_event_string() argument
277 dwc3_ep0_state_string(ep0state)); in dwc3_ep_event_string()
372 u32 ep0state) in dwc3_decode_event() argument
381 return dwc3_ep_event_string(str, size, &evt.depevt, ep0state); in dwc3_decode_event()
H A Dep0.c112 if (dwc->ep0state != EP0_DATA_PHASE) { in __dwc3_gadget_ep0_queue()
136 if (dwc->ep0state == EP0_STATUS_PHASE) in __dwc3_gadget_ep0_queue()
178 dwc->ep0state = EP0_DATA_PHASE; in __dwc3_gadget_ep0_queue()
244 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_stall_and_restart()
955 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_complete_status()
968 switch (dwc->ep0state) { in dwc3_ep0_xfer_complete()
981 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); in dwc3_ep0_xfer_complete()
1103 if (dwc->ep0state != EP0_STATUS_PHASE) in dwc3_ep0_send_delayed_status()
1170 dwc->ep0state = EP0_STATUS_PHASE; in dwc3_ep0_xfernotready()
H A Dtrace.h54 __field(u32, ep0state)
59 __entry->ep0state = dwc->ep0state;
63 __entry->event, __entry->ep0state))
H A Dgadget.c1842 if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) { in __dwc3_stop_active_transfer()
2667 if (dwc->ep0state != EP0_SETUP_PHASE && in dwc3_gadget_soft_disconnect()
2668 dwc->ep0state != EP0_UNCONNECTED) { in dwc3_gadget_soft_disconnect()
2912 dwc->ep0state = EP0_SETUP_PHASE; in __dwc3_gadget_start()
3960 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE) in dwc3_stop_active_transfer()
3975 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) { in dwc3_stop_active_transfer()
4052 if (dwc->ep0state != EP0_SETUP_PHASE) { in dwc3_gadget_disconnect_interrupt()
4056 if (dwc->ep0state == EP0_DATA_PHASE) in dwc3_gadget_disconnect_interrupt()
4115 if (dwc->ep0state != EP0_SETUP_PHASE) { in dwc3_gadget_reset_interrupt()
4119 if (dwc->ep0state == EP0_DATA_PHASE) in dwc3_gadget_reset_interrupt()
/OK3568_Linux_fs/u-boot/drivers/usb/dwc3/
H A Dep0.c135 if (dwc->ep0state != EP0_DATA_PHASE) { in __dwc3_gadget_ep0_queue()
159 if (dwc->ep0state == EP0_STATUS_PHASE) in __dwc3_gadget_ep0_queue()
203 dwc->ep0state = EP0_DATA_PHASE; in __dwc3_gadget_ep0_queue()
240 dwc3_ep0_state_string(dwc->ep0state)); in dwc3_gadget_ep0_queue()
271 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_stall_and_restart()
899 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_complete_status()
912 switch (dwc->ep0state) { in dwc3_ep0_xfer_complete()
928 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); in dwc3_ep0_xfer_complete()
1078 dwc->ep0state = EP0_STATUS_PHASE; in dwc3_ep0_xfernotready()
1098 dwc3_ep0_state_string(dwc->ep0state)); in dwc3_ep0_interrupt()
/OK3568_Linux_fs/kernel/drivers/staging/emxx_udc/
H A Demxx_udc.c1182 switch (udc->ep0state) { in _nbu2ss_start_transfer()
1611 udc->ep0state = EP0_IN_STATUS_PHASE; in _nbu2ss_decode_request()
1615 udc->ep0state = EP0_IN_DATA_PHASE; in _nbu2ss_decode_request()
1617 udc->ep0state = EP0_OUT_DATA_PHASE; in _nbu2ss_decode_request()
1652 if (udc->ep0state == EP0_IN_STATUS_PHASE) { in _nbu2ss_decode_request()
1667 udc->ep0state = EP0_IDLE; in _nbu2ss_decode_request()
1688 udc->ep0state = EP0_OUT_STATUS_PAHSE; in _nbu2ss_ep0_in_data_stage()
1708 udc->ep0state = EP0_IN_STATUS_PHASE; in _nbu2ss_ep0_out_data_stage()
1736 udc->ep0state = EP0_IDLE; in _nbu2ss_ep0_status_stage()
1766 switch (udc->ep0state) { in _nbu2ss_ep0_int()
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H A Demxx_udc.h523 enum ep0_state ep0state; member

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