1 /*
2 * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
3 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
4 *
5 * Copyright (C) 2009 for Samsung Electronics
6 *
7 * BSP Support for Samsung's UDC driver
8 * available at:
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
10 *
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
13 *
14 * Ported to u-boot:
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
17 *
18 * SPDX-License-Identifier: GPL-2.0+
19 */
20
21 static u8 clear_feature_num;
22 int clear_feature_flag;
23
24 /* Bulk-Only Mass Storage Reset (class-specific request) */
25 #define GET_MAX_LUN_REQUEST 0xFE
26 #define BOT_RESET_REQUEST 0xFF
27
dwc2_udc_ep0_zlp(struct dwc2_udc * dev)28 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
29 {
30 u32 ep_ctrl;
31
32 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
33 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
34
35 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
36 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
37 ®->in_endp[EP0_CON].diepctl);
38
39 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
40 __func__, readl(®->in_endp[EP0_CON].diepctl));
41 dev->ep0state = WAIT_FOR_IN_COMPLETE;
42 }
43
dwc2_udc_pre_setup(void)44 static void dwc2_udc_pre_setup(void)
45 {
46 u32 ep_ctrl;
47
48 debug_cond(DEBUG_IN_EP,
49 "%s : Prepare Setup packets.\n", __func__);
50
51 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
52 ®->out_endp[EP0_CON].doeptsiz);
53 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
54
55 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
56 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
57
58 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
59 __func__, readl(®->in_endp[EP0_CON].diepctl));
60 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
61 __func__, readl(®->out_endp[EP0_CON].doepctl));
62
63 }
64
dwc2_ep0_complete_out(void)65 static inline void dwc2_ep0_complete_out(void)
66 {
67 u32 ep_ctrl;
68
69 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
70 __func__, readl(®->in_endp[EP0_CON].diepctl));
71 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
72 __func__, readl(®->out_endp[EP0_CON].doepctl));
73
74 debug_cond(DEBUG_IN_EP,
75 "%s : Prepare Complete Out packet.\n", __func__);
76
77 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
78 ®->out_endp[EP0_CON].doeptsiz);
79 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
80
81 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
82 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
83 ®->out_endp[EP0_CON].doepctl);
84
85 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
86 __func__, readl(®->in_endp[EP0_CON].diepctl));
87 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
88 __func__, readl(®->out_endp[EP0_CON].doepctl));
89
90 }
91
92
setdma_rx(struct dwc2_ep * ep,struct dwc2_request * req)93 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
94 {
95 u32 *buf, ctrl;
96 u32 length, pktcnt;
97 u32 ep_num = ep_index(ep);
98
99 buf = req->req.buf + req->req.actual;
100 length = min_t(u32, req->req.length - req->req.actual,
101 ep_num ? DOEPT_SIZ_XFER_SIZE_MAX_EP : ep->ep.maxpacket);
102
103 ep->len = length;
104 ep->dma_buf = buf;
105
106 if (ep_num == EP0_CON || length == 0)
107 pktcnt = 1;
108 else
109 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
110
111 ctrl = readl(®->out_endp[ep_num].doepctl);
112
113 invalidate_dcache_range((unsigned long) ep->dma_buf,
114 (unsigned long) ep->dma_buf +
115 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
116
117 writel((unsigned long) ep->dma_buf, ®->out_endp[ep_num].doepdma);
118 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
119 ®->out_endp[ep_num].doeptsiz);
120 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
121
122 debug_cond(DEBUG_OUT_EP != 0,
123 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
124 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
125 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
126 __func__, ep_num,
127 readl(®->out_endp[ep_num].doepdma),
128 readl(®->out_endp[ep_num].doeptsiz),
129 readl(®->out_endp[ep_num].doepctl),
130 buf, pktcnt, length);
131 return 0;
132
133 }
134
setdma_tx(struct dwc2_ep * ep,struct dwc2_request * req)135 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
136 {
137 u32 *buf, ctrl = 0;
138 u32 length, pktcnt;
139 u32 ep_num = ep_index(ep);
140
141 buf = req->req.buf + req->req.actual;
142 length = req->req.length - req->req.actual;
143
144 if (ep_num == EP0_CON)
145 length = min(length, (u32)ep_maxpacket(ep));
146
147 ep->len = length;
148 ep->dma_buf = buf;
149
150 flush_dcache_range((unsigned long) ep->dma_buf,
151 (unsigned long) ep->dma_buf +
152 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
153
154 if (length == 0)
155 pktcnt = 1;
156 else
157 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
158
159 /* Flush the endpoint's Tx FIFO */
160 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
161 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
162 while (readl(®->grstctl) & TX_FIFO_FLUSH)
163 ;
164
165 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma);
166 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
167 ®->in_endp[ep_num].dieptsiz);
168
169 ctrl = readl(®->in_endp[ep_num].diepctl);
170
171 /* Write the FIFO number to be used for this endpoint */
172 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
173 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
174
175 /* Clear reserved (Next EP) bits */
176 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
177
178 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
179
180 debug_cond(DEBUG_IN_EP,
181 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
182 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
183 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
184 __func__, ep_num,
185 readl(®->in_endp[ep_num].diepdma),
186 readl(®->in_endp[ep_num].dieptsiz),
187 readl(®->in_endp[ep_num].diepctl),
188 buf, pktcnt, length);
189
190 return length;
191 }
192
complete_rx(struct dwc2_udc * dev,u8 ep_num)193 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
194 {
195 struct dwc2_ep *ep = &dev->ep[ep_num];
196 struct dwc2_request *req = NULL;
197 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
198
199 if (list_empty(&ep->queue)) {
200 debug_cond(DEBUG_OUT_EP != 0,
201 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
202 __func__, ep_num);
203 return;
204
205 }
206
207 req = list_entry(ep->queue.next, struct dwc2_request, queue);
208 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
209
210 if (ep_num == EP0_CON)
211 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
212 else
213 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
214
215 xfer_size = ep->len - xfer_size;
216
217 /*
218 * NOTE:
219 *
220 * Please be careful with proper buffer allocation for USB request,
221 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
222 * with starting address, but also its size shall be a cache line
223 * multiplication.
224 *
225 * This will prevent from corruption of data allocated immediatelly
226 * before or after the buffer.
227 *
228 * For armv7, the cache_v7.c provides proper code to emit "ERROR"
229 * message to warn users.
230 */
231 invalidate_dcache_range((unsigned long) ep->dma_buf,
232 (unsigned long) ep->dma_buf +
233 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
234
235 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
236 is_short = !!(xfer_size % ep->ep.maxpacket);
237
238 debug_cond(DEBUG_OUT_EP != 0,
239 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
240 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
241 __func__, ep_num, req->req.actual, req->req.length,
242 is_short, ep_tsr, req->req.length - req->req.actual);
243
244 if (is_short || req->req.actual == req->req.length) {
245 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
246 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
247 dwc2_udc_ep0_zlp(dev);
248 /* packet will be completed in complete_tx() */
249 dev->ep0state = WAIT_FOR_IN_COMPLETE;
250 } else {
251 done(ep, req, 0);
252
253 if (!list_empty(&ep->queue)) {
254 req = list_entry(ep->queue.next,
255 struct dwc2_request, queue);
256 debug_cond(DEBUG_OUT_EP != 0,
257 "%s: Next Rx request start...\n",
258 __func__);
259 setdma_rx(ep, req);
260 }
261 }
262 } else
263 setdma_rx(ep, req);
264 }
265
complete_tx(struct dwc2_udc * dev,u8 ep_num)266 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
267 {
268 struct dwc2_ep *ep = &dev->ep[ep_num];
269 struct dwc2_request *req;
270 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
271 u32 last;
272
273 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
274 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
275 dwc2_ep0_complete_out();
276 return;
277 }
278
279 if (list_empty(&ep->queue)) {
280 debug_cond(DEBUG_IN_EP,
281 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
282 __func__, ep_num);
283 return;
284
285 }
286
287 req = list_entry(ep->queue.next, struct dwc2_request, queue);
288
289 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
290
291 xfer_size = ep->len;
292 is_short = (xfer_size < ep->ep.maxpacket);
293 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
294
295 debug_cond(DEBUG_IN_EP,
296 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
297 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
298 __func__, ep_num, req->req.actual, req->req.length,
299 is_short, ep_tsr, req->req.length - req->req.actual);
300
301 if (ep_num == 0) {
302 if (dev->ep0state == DATA_STATE_XMIT) {
303 debug_cond(DEBUG_IN_EP,
304 "%s: ep_num = %d, ep0stat =="
305 "DATA_STATE_XMIT\n",
306 __func__, ep_num);
307 last = write_fifo_ep0(ep, req);
308 if (last)
309 dev->ep0state = WAIT_FOR_COMPLETE;
310 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
311 debug_cond(DEBUG_IN_EP,
312 "%s: ep_num = %d, completing request\n",
313 __func__, ep_num);
314 done(ep, req, 0);
315 dev->ep0state = WAIT_FOR_SETUP;
316 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
317 debug_cond(DEBUG_IN_EP,
318 "%s: ep_num = %d, completing request\n",
319 __func__, ep_num);
320 done(ep, req, 0);
321 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
322 dwc2_ep0_complete_out();
323 } else {
324 debug_cond(DEBUG_IN_EP,
325 "%s: ep_num = %d, invalid ep state\n",
326 __func__, ep_num);
327 }
328 return;
329 }
330
331 if (req->req.actual == req->req.length)
332 done(ep, req, 0);
333
334 if (!list_empty(&ep->queue)) {
335 req = list_entry(ep->queue.next, struct dwc2_request, queue);
336 debug_cond(DEBUG_IN_EP,
337 "%s: Next Tx request start...\n", __func__);
338 setdma_tx(ep, req);
339 }
340 }
341
dwc2_udc_check_tx_queue(struct dwc2_udc * dev,u8 ep_num)342 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
343 {
344 struct dwc2_ep *ep = &dev->ep[ep_num];
345 struct dwc2_request *req;
346
347 debug_cond(DEBUG_IN_EP,
348 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
349
350 if (!list_empty(&ep->queue)) {
351 req = list_entry(ep->queue.next, struct dwc2_request, queue);
352 debug_cond(DEBUG_IN_EP,
353 "%s: Next Tx request(0x%p) start...\n",
354 __func__, req);
355
356 if (ep_is_in(ep))
357 setdma_tx(ep, req);
358 else
359 setdma_rx(ep, req);
360 } else {
361 debug_cond(DEBUG_IN_EP,
362 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
363
364 return;
365 }
366
367 }
368
process_ep_in_intr(struct dwc2_udc * dev)369 static void process_ep_in_intr(struct dwc2_udc *dev)
370 {
371 u32 ep_intr, ep_intr_status;
372 u8 ep_num = 0;
373
374 ep_intr = readl(®->daint);
375 debug_cond(DEBUG_IN_EP,
376 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
377
378 ep_intr &= DAINT_MASK;
379
380 while (ep_intr) {
381 if (ep_intr & DAINT_IN_EP_INT(1)) {
382 ep_intr_status = readl(®->in_endp[ep_num].diepint);
383 debug_cond(DEBUG_IN_EP,
384 "\tEP%d-IN : DIEPINT = 0x%x\n",
385 ep_num, ep_intr_status);
386
387 /* Interrupt Clear */
388 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
389
390 if (ep_intr_status & TRANSFER_DONE) {
391 complete_tx(dev, ep_num);
392
393 if (ep_num == 0) {
394 if (dev->ep0state ==
395 WAIT_FOR_IN_COMPLETE)
396 dev->ep0state = WAIT_FOR_SETUP;
397
398 if (dev->ep0state == WAIT_FOR_SETUP)
399 dwc2_udc_pre_setup();
400
401 /* continue transfer after
402 set_clear_halt for DMA mode */
403 if (clear_feature_flag == 1) {
404 dwc2_udc_check_tx_queue(dev,
405 clear_feature_num);
406 clear_feature_flag = 0;
407 }
408 }
409 }
410 }
411 ep_num++;
412 ep_intr >>= 1;
413 }
414 }
415
process_ep_out_intr(struct dwc2_udc * dev)416 static void process_ep_out_intr(struct dwc2_udc *dev)
417 {
418 u32 ep_intr, ep_intr_status;
419 u8 ep_num = 0;
420
421 ep_intr = readl(®->daint);
422 debug_cond(DEBUG_OUT_EP != 0,
423 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
424 __func__, ep_intr);
425
426 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
427
428 while (ep_intr) {
429 if (ep_intr & 0x1) {
430 ep_intr_status = readl(®->out_endp[ep_num].doepint);
431 debug_cond(DEBUG_OUT_EP != 0,
432 "\tEP%d-OUT : DOEPINT = 0x%x\n",
433 ep_num, ep_intr_status);
434
435 /* Interrupt Clear */
436 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
437
438 if (ep_num == 0) {
439 if (ep_intr_status & TRANSFER_DONE) {
440 if (dev->ep0state !=
441 WAIT_FOR_OUT_COMPLETE)
442 complete_rx(dev, ep_num);
443 else {
444 dev->ep0state = WAIT_FOR_SETUP;
445 dwc2_udc_pre_setup();
446 }
447 }
448
449 if (ep_intr_status &
450 CTRL_OUT_EP_SETUP_PHASE_DONE) {
451 debug_cond(DEBUG_OUT_EP != 0,
452 "SETUP packet arrived\n");
453 dwc2_handle_ep0(dev);
454 }
455 } else {
456 if (ep_intr_status & TRANSFER_DONE)
457 complete_rx(dev, ep_num);
458 }
459 }
460 ep_num++;
461 ep_intr >>= 1;
462 }
463 }
464
465 /*
466 * usb client interrupt handler.
467 */
dwc2_udc_irq(int irq,void * _dev)468 static int dwc2_udc_irq(int irq, void *_dev)
469 {
470 struct dwc2_udc *dev = _dev;
471 u32 intr_status, gotgint;
472 u32 usb_status, gintmsk;
473 unsigned long flags = 0;
474
475 spin_lock_irqsave(&dev->lock, flags);
476
477 intr_status = readl(®->gintsts);
478 gintmsk = readl(®->gintmsk);
479
480 debug_cond(DEBUG_ISR,
481 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
482 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
483 __func__, intr_status, state_names[dev->ep0state], gintmsk,
484 readl(®->daint), readl(®->daintmsk));
485
486 if (!intr_status) {
487 spin_unlock_irqrestore(&dev->lock, flags);
488 return IRQ_HANDLED;
489 }
490
491 if (intr_status & INT_ENUMDONE) {
492 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
493
494 writel(INT_ENUMDONE, ®->gintsts);
495 usb_status = (readl(®->dsts) & 0x6);
496
497 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
498 debug_cond(DEBUG_ISR,
499 "\t\tFull Speed Detection\n");
500 set_max_pktsize(dev, USB_SPEED_FULL);
501
502 } else {
503 debug_cond(DEBUG_ISR,
504 "\t\tHigh Speed Detection : 0x%x\n",
505 usb_status);
506 set_max_pktsize(dev, USB_SPEED_HIGH);
507 }
508 }
509
510 if (intr_status & INT_EARLY_SUSPEND) {
511 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
512 writel(INT_EARLY_SUSPEND, ®->gintsts);
513 }
514
515 if (intr_status & INT_SUSPEND) {
516 usb_status = readl(®->dsts);
517 debug_cond(DEBUG_ISR,
518 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
519 writel(INT_SUSPEND, ®->gintsts);
520
521 if (dev->gadget.speed != USB_SPEED_UNKNOWN
522 && dev->driver) {
523 if (dev->driver->suspend)
524 dev->driver->suspend(&dev->gadget);
525 }
526 }
527
528 if (intr_status & INT_OTG) {
529 gotgint = readl(®->gotgint);
530 debug_cond(DEBUG_ISR,
531 "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
532
533 if (gotgint & GOTGINT_SES_END_DET) {
534 debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
535 /* Let gadget detect disconnected state */
536 if (dev->driver->disconnect) {
537 spin_unlock_irqrestore(&dev->lock, flags);
538 dev->driver->disconnect(&dev->gadget);
539 spin_lock_irqsave(&dev->lock, flags);
540 }
541 }
542 writel(gotgint, ®->gotgint);
543 }
544
545 if (intr_status & INT_RESUME) {
546 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
547 writel(INT_RESUME, ®->gintsts);
548
549 if (dev->gadget.speed != USB_SPEED_UNKNOWN
550 && dev->driver
551 && dev->driver->resume) {
552
553 dev->driver->resume(&dev->gadget);
554 }
555 }
556
557 if (intr_status & INT_RESET) {
558 u32 temp;
559 u32 connected = dev->connected;
560
561 usb_status = readl(®->gotgctl);
562 debug_cond(DEBUG_ISR,
563 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
564 writel(INT_RESET, ®->gintsts);
565
566 if ((usb_status & 0xc0000) == (0x3 << 18)) {
567 if (reset_available) {
568 debug_cond(DEBUG_ISR,
569 "\t\tOTG core got reset (%d)!!\n",
570 reset_available);
571 /* Reset device address to zero */
572 temp = readl(®->dcfg);
573 temp &= ~DCFG_DEVADDR_MASK;
574 writel(temp, ®->dcfg);
575
576 /* Soft reset the core if connected */
577 if (connected)
578 reconfig_usbd(dev);
579
580 dev->ep0state = WAIT_FOR_SETUP;
581 reset_available = 0;
582 dwc2_udc_pre_setup();
583 } else
584 reset_available = 1;
585
586 } else {
587 reset_available = 1;
588 debug_cond(DEBUG_ISR,
589 "\t\tRESET handling skipped\n");
590 }
591 }
592
593 if (intr_status & INT_IN_EP)
594 process_ep_in_intr(dev);
595
596 if (intr_status & INT_OUT_EP)
597 process_ep_out_intr(dev);
598
599 spin_unlock_irqrestore(&dev->lock, flags);
600
601 return IRQ_HANDLED;
602 }
603
604 /** Queue one request
605 * Kickstart transfer if needed
606 */
dwc2_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)607 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
608 gfp_t gfp_flags)
609 {
610 struct dwc2_request *req;
611 struct dwc2_ep *ep;
612 struct dwc2_udc *dev;
613 unsigned long flags = 0;
614 u32 ep_num, gintsts;
615
616 req = container_of(_req, struct dwc2_request, req);
617 if (unlikely(!_req || !_req->complete || !_req->buf
618 || !list_empty(&req->queue))) {
619
620 debug("%s: bad params\n", __func__);
621 return -EINVAL;
622 }
623
624 ep = container_of(_ep, struct dwc2_ep, ep);
625
626 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
627
628 debug("%s: bad ep: %s, %d, %p\n", __func__,
629 ep->ep.name, !ep->desc, _ep);
630 return -EINVAL;
631 }
632
633 ep_num = ep_index(ep);
634 dev = ep->dev;
635 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
636
637 debug("%s: bogus device state %p\n", __func__, dev->driver);
638 return -ESHUTDOWN;
639 }
640
641 spin_lock_irqsave(&dev->lock, flags);
642
643 _req->status = -EINPROGRESS;
644 _req->actual = 0;
645
646 /* kickstart this i/o queue? */
647 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
648 "Q empty = %d, stopped = %d\n",
649 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
650 _req, _req->length, _req->buf,
651 list_empty(&ep->queue), ep->stopped);
652
653 #ifdef DEBUG
654 {
655 int i, len = _req->length;
656
657 printf("pkt = ");
658 if (len > 64)
659 len = 64;
660 for (i = 0; i < len; i++) {
661 printf("%02x", ((u8 *)_req->buf)[i]);
662 if ((i & 7) == 7)
663 printf(" ");
664 }
665 printf("\n");
666 }
667 #endif
668
669 if (list_empty(&ep->queue) && !ep->stopped) {
670
671 if (ep_num == 0) {
672 /* EP0 */
673 list_add_tail(&req->queue, &ep->queue);
674 dwc2_ep0_kick(dev, ep);
675 req = 0;
676
677 } else if (ep_is_in(ep)) {
678 gintsts = readl(®->gintsts);
679 debug_cond(DEBUG_IN_EP,
680 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
681 __func__, gintsts);
682
683 setdma_tx(ep, req);
684 } else {
685 gintsts = readl(®->gintsts);
686 debug_cond(DEBUG_OUT_EP != 0,
687 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
688 __func__, gintsts);
689
690 setdma_rx(ep, req);
691 }
692 }
693
694 /* pio or dma irq handler advances the queue. */
695 if (likely(req != 0))
696 list_add_tail(&req->queue, &ep->queue);
697
698 spin_unlock_irqrestore(&dev->lock, flags);
699
700 return 0;
701 }
702
703 /****************************************************************/
704 /* End Point 0 related functions */
705 /****************************************************************/
706
707 /* return: 0 = still running, 1 = completed, negative = errno */
write_fifo_ep0(struct dwc2_ep * ep,struct dwc2_request * req)708 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
709 {
710 u32 max;
711 unsigned count;
712 int is_last;
713
714 max = ep_maxpacket(ep);
715
716 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
717
718 count = setdma_tx(ep, req);
719
720 /* last packet is usually short (or a zlp) */
721 if (likely(count != max))
722 is_last = 1;
723 else {
724 if (likely(req->req.length != req->req.actual + count)
725 || req->req.zero)
726 is_last = 0;
727 else
728 is_last = 1;
729 }
730
731 debug_cond(DEBUG_EP0 != 0,
732 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
733 ep->ep.name, count,
734 is_last ? "/L" : "",
735 req->req.length - req->req.actual - count, req);
736
737 /* requests complete when all IN data is in the FIFO */
738 if (is_last) {
739 ep->dev->ep0state = WAIT_FOR_SETUP;
740 return 1;
741 }
742
743 return 0;
744 }
745
dwc2_fifo_read(struct dwc2_ep * ep,void * cp,int max)746 static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
747 {
748 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
749 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
750
751 debug_cond(DEBUG_EP0 != 0,
752 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
753 max, ep_index(ep), cp);
754
755 return max;
756 }
757
758 /**
759 * udc_set_address - set the USB address for this device
760 * @address:
761 *
762 * Called from control endpoint function
763 * after it decodes a set address setup packet.
764 */
udc_set_address(struct dwc2_udc * dev,unsigned char address)765 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
766 {
767 u32 ctrl = readl(®->dcfg);
768 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
769
770 dwc2_udc_ep0_zlp(dev);
771
772 debug_cond(DEBUG_EP0 != 0,
773 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
774 __func__, address, readl(®->dcfg));
775
776 dev->usb_address = address;
777 }
778
dwc2_udc_ep0_set_stall(struct dwc2_ep * ep)779 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
780 {
781 struct dwc2_udc *dev;
782 u32 ep_ctrl = 0;
783
784 dev = ep->dev;
785 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
786
787 /* set the disable and stall bits */
788 if (ep_ctrl & DEPCTL_EPENA)
789 ep_ctrl |= DEPCTL_EPDIS;
790
791 ep_ctrl |= DEPCTL_STALL;
792
793 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
794
795 debug_cond(DEBUG_EP0 != 0,
796 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
797 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
798 /*
799 * The application can only set this bit, and the core clears it,
800 * when a SETUP token is received for this endpoint
801 */
802 dev->ep0state = WAIT_FOR_SETUP;
803
804 dwc2_udc_pre_setup();
805 }
806
dwc2_ep0_read(struct dwc2_udc * dev)807 static void dwc2_ep0_read(struct dwc2_udc *dev)
808 {
809 struct dwc2_request *req;
810 struct dwc2_ep *ep = &dev->ep[0];
811
812 if (!list_empty(&ep->queue)) {
813 req = list_entry(ep->queue.next, struct dwc2_request, queue);
814
815 } else {
816 debug("%s: ---> BUG\n", __func__);
817 BUG();
818 return;
819 }
820
821 debug_cond(DEBUG_EP0 != 0,
822 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
823 __func__, req, req->req.length, req->req.actual);
824
825 if (req->req.length == 0) {
826 /* zlp for Set_configuration, Set_interface,
827 * or Bulk-Only mass storge reset */
828
829 ep->len = 0;
830 dwc2_udc_ep0_zlp(dev);
831
832 debug_cond(DEBUG_EP0 != 0,
833 "%s: req.length = 0, bRequest = %d\n",
834 __func__, usb_ctrl->bRequest);
835 return;
836 }
837
838 setdma_rx(ep, req);
839 }
840
841 /*
842 * DATA_STATE_XMIT
843 */
dwc2_ep0_write(struct dwc2_udc * dev)844 static int dwc2_ep0_write(struct dwc2_udc *dev)
845 {
846 struct dwc2_request *req;
847 struct dwc2_ep *ep = &dev->ep[0];
848 int ret, need_zlp = 0;
849
850 if (list_empty(&ep->queue))
851 req = 0;
852 else
853 req = list_entry(ep->queue.next, struct dwc2_request, queue);
854
855 if (!req) {
856 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
857 return 0;
858 }
859
860 debug_cond(DEBUG_EP0 != 0,
861 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
862 __func__, req, req->req.length, req->req.actual);
863
864 if (req->req.length - req->req.actual == ep0_fifo_size) {
865 /* Next write will end with the packet size, */
866 /* so we need Zero-length-packet */
867 need_zlp = 1;
868 }
869
870 ret = write_fifo_ep0(ep, req);
871
872 if ((ret == 1) && !need_zlp) {
873 /* Last packet */
874 dev->ep0state = WAIT_FOR_COMPLETE;
875 debug_cond(DEBUG_EP0 != 0,
876 "%s: finished, waiting for status\n", __func__);
877
878 } else {
879 dev->ep0state = DATA_STATE_XMIT;
880 debug_cond(DEBUG_EP0 != 0,
881 "%s: not finished\n", __func__);
882 }
883
884 return 1;
885 }
886
dwc2_udc_get_status(struct dwc2_udc * dev,struct usb_ctrlrequest * crq)887 static int dwc2_udc_get_status(struct dwc2_udc *dev,
888 struct usb_ctrlrequest *crq)
889 {
890 u8 ep_num = crq->wIndex & 0x7F;
891 u16 g_status = 0;
892 u32 ep_ctrl;
893
894 debug_cond(DEBUG_SETUP != 0,
895 "%s: *** USB_REQ_GET_STATUS\n", __func__);
896 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
897 switch (crq->bRequestType & USB_RECIP_MASK) {
898 case USB_RECIP_INTERFACE:
899 g_status = 0;
900 debug_cond(DEBUG_SETUP != 0,
901 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
902 g_status);
903 break;
904
905 case USB_RECIP_DEVICE:
906 g_status = 0x1; /* Self powered */
907 debug_cond(DEBUG_SETUP != 0,
908 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
909 g_status);
910 break;
911
912 case USB_RECIP_ENDPOINT:
913 if (crq->wLength > 2) {
914 debug_cond(DEBUG_SETUP != 0,
915 "\tGET_STATUS:Not support EP or wLength\n");
916 return 1;
917 }
918
919 g_status = dev->ep[ep_num].stopped;
920 debug_cond(DEBUG_SETUP != 0,
921 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
922 g_status);
923
924 break;
925
926 default:
927 return 1;
928 }
929
930 memcpy(usb_ctrl, &g_status, sizeof(g_status));
931
932 flush_dcache_range((unsigned long) usb_ctrl,
933 (unsigned long) usb_ctrl +
934 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
935
936 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
937 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
938 ®->in_endp[EP0_CON].dieptsiz);
939
940 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
941 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
942 ®->in_endp[EP0_CON].diepctl);
943 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
944
945 return 0;
946 }
947
dwc2_udc_set_nak(struct dwc2_ep * ep)948 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
949 {
950 u8 ep_num;
951 u32 ep_ctrl = 0;
952
953 ep_num = ep_index(ep);
954 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
955
956 if (ep_is_in(ep)) {
957 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
958 ep_ctrl |= DEPCTL_SNAK;
959 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
960 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
961 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
962 } else {
963 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
964 ep_ctrl |= DEPCTL_SNAK;
965 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
966 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
967 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
968 }
969
970 return;
971 }
972
973
dwc2_udc_ep_set_stall(struct dwc2_ep * ep)974 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
975 {
976 u8 ep_num;
977 u32 ep_ctrl = 0;
978
979 ep_num = ep_index(ep);
980 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
981
982 if (ep_is_in(ep)) {
983 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
984
985 /* set the disable and stall bits */
986 if (ep_ctrl & DEPCTL_EPENA)
987 ep_ctrl |= DEPCTL_EPDIS;
988
989 ep_ctrl |= DEPCTL_STALL;
990
991 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
992 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
993 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
994
995 } else {
996 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
997
998 /* set the stall bit */
999 ep_ctrl |= DEPCTL_STALL;
1000
1001 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1002 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
1003 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1004 }
1005
1006 return;
1007 }
1008
dwc2_udc_ep_clear_stall(struct dwc2_ep * ep)1009 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
1010 {
1011 u8 ep_num;
1012 u32 ep_ctrl = 0;
1013
1014 ep_num = ep_index(ep);
1015 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1016
1017 if (ep_is_in(ep)) {
1018 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1019
1020 /* clear stall bit */
1021 ep_ctrl &= ~DEPCTL_STALL;
1022
1023 /*
1024 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1025 * of whether an endpoint has the Halt feature set, a
1026 * ClearFeature(ENDPOINT_HALT) request always results in the
1027 * data toggle being reinitialized to DATA0.
1028 */
1029 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1030 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1031 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1032 }
1033
1034 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1035 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1036 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1037
1038 } else {
1039 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1040
1041 /* clear stall bit */
1042 ep_ctrl &= ~DEPCTL_STALL;
1043
1044 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1045 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1046 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1047 }
1048
1049 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1050 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1051 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1052 }
1053
1054 return;
1055 }
1056
dwc2_udc_set_halt(struct usb_ep * _ep,int value)1057 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1058 {
1059 struct dwc2_ep *ep;
1060 struct dwc2_udc *dev;
1061 unsigned long flags = 0;
1062 u8 ep_num;
1063
1064 ep = container_of(_ep, struct dwc2_ep, ep);
1065 ep_num = ep_index(ep);
1066
1067 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1068 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1069 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1070 return -EINVAL;
1071 }
1072
1073 /* Attempt to halt IN ep will fail if any transfer requests
1074 * are still queue */
1075 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1076 debug("%s: %s queue not empty, req = %p\n",
1077 __func__, ep->ep.name,
1078 list_entry(ep->queue.next, struct dwc2_request, queue));
1079
1080 return -EAGAIN;
1081 }
1082
1083 dev = ep->dev;
1084 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1085
1086 spin_lock_irqsave(&dev->lock, flags);
1087
1088 if (value == 0) {
1089 ep->stopped = 0;
1090 dwc2_udc_ep_clear_stall(ep);
1091 } else {
1092 if (ep_num == 0)
1093 dev->ep0state = WAIT_FOR_SETUP;
1094
1095 ep->stopped = 1;
1096 dwc2_udc_ep_set_stall(ep);
1097 }
1098
1099 spin_unlock_irqrestore(&dev->lock, flags);
1100
1101 return 0;
1102 }
1103
dwc2_udc_ep_activate(struct dwc2_ep * ep)1104 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1105 {
1106 u8 ep_num;
1107 u32 ep_ctrl = 0, daintmsk = 0;
1108
1109 ep_num = ep_index(ep);
1110
1111 /* Read DEPCTLn register */
1112 if (ep_is_in(ep)) {
1113 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1114 daintmsk = 1 << ep_num;
1115 } else {
1116 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1117 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1118 }
1119
1120 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1121 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1122
1123 /* If the EP is already active don't change the EP Control
1124 * register. */
1125 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1126 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1127 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1128 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1129 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1130 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1131
1132 if (ep_is_in(ep)) {
1133 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1134 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1135 __func__, ep_num, ep_num,
1136 readl(®->in_endp[ep_num].diepctl));
1137 } else {
1138 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1139 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1140 __func__, ep_num, ep_num,
1141 readl(®->out_endp[ep_num].doepctl));
1142 }
1143 }
1144
1145 /* Unmask EP Interrtupt */
1146 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1147 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1148
1149 }
1150
dwc2_udc_clear_feature(struct usb_ep * _ep)1151 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1152 {
1153 struct dwc2_udc *dev;
1154 struct dwc2_ep *ep;
1155 u8 ep_num;
1156
1157 ep = container_of(_ep, struct dwc2_ep, ep);
1158 ep_num = ep_index(ep);
1159
1160 dev = ep->dev;
1161 debug_cond(DEBUG_SETUP != 0,
1162 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1163 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1164
1165 if (usb_ctrl->wLength != 0) {
1166 debug_cond(DEBUG_SETUP != 0,
1167 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1168 return 1;
1169 }
1170
1171 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1172 case USB_RECIP_DEVICE:
1173 switch (usb_ctrl->wValue) {
1174 case USB_DEVICE_REMOTE_WAKEUP:
1175 debug_cond(DEBUG_SETUP != 0,
1176 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1177 break;
1178
1179 case USB_DEVICE_TEST_MODE:
1180 debug_cond(DEBUG_SETUP != 0,
1181 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1182 /** @todo Add CLEAR_FEATURE for TEST modes. */
1183 break;
1184 }
1185
1186 dwc2_udc_ep0_zlp(dev);
1187 break;
1188
1189 case USB_RECIP_ENDPOINT:
1190 debug_cond(DEBUG_SETUP != 0,
1191 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1192 usb_ctrl->wValue);
1193
1194 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1195 if (ep_num == 0) {
1196 dwc2_udc_ep0_set_stall(ep);
1197 return 0;
1198 }
1199
1200 dwc2_udc_ep0_zlp(dev);
1201
1202 dwc2_udc_ep_clear_stall(ep);
1203 dwc2_udc_ep_activate(ep);
1204 ep->stopped = 0;
1205
1206 clear_feature_num = ep_num;
1207 clear_feature_flag = 1;
1208 }
1209 break;
1210 }
1211
1212 return 0;
1213 }
1214
dwc2_udc_set_feature(struct usb_ep * _ep)1215 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1216 {
1217 struct dwc2_udc *dev;
1218 struct dwc2_ep *ep;
1219 u8 ep_num;
1220
1221 ep = container_of(_ep, struct dwc2_ep, ep);
1222 ep_num = ep_index(ep);
1223 dev = ep->dev;
1224
1225 debug_cond(DEBUG_SETUP != 0,
1226 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1227 __func__, ep_num);
1228
1229 if (usb_ctrl->wLength != 0) {
1230 debug_cond(DEBUG_SETUP != 0,
1231 "\tSET_FEATURE: wLength is not zero.....\n");
1232 return 1;
1233 }
1234
1235 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1236 case USB_RECIP_DEVICE:
1237 switch (usb_ctrl->wValue) {
1238 case USB_DEVICE_REMOTE_WAKEUP:
1239 debug_cond(DEBUG_SETUP != 0,
1240 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1241 break;
1242 case USB_DEVICE_B_HNP_ENABLE:
1243 debug_cond(DEBUG_SETUP != 0,
1244 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1245 break;
1246
1247 case USB_DEVICE_A_HNP_SUPPORT:
1248 /* RH port supports HNP */
1249 debug_cond(DEBUG_SETUP != 0,
1250 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1251 break;
1252
1253 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1254 /* other RH port does */
1255 debug_cond(DEBUG_SETUP != 0,
1256 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1257 break;
1258 }
1259
1260 dwc2_udc_ep0_zlp(dev);
1261 return 0;
1262
1263 case USB_RECIP_INTERFACE:
1264 debug_cond(DEBUG_SETUP != 0,
1265 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1266 break;
1267
1268 case USB_RECIP_ENDPOINT:
1269 debug_cond(DEBUG_SETUP != 0,
1270 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1271 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1272 if (ep_num == 0) {
1273 dwc2_udc_ep0_set_stall(ep);
1274 return 0;
1275 }
1276 ep->stopped = 1;
1277 dwc2_udc_ep_set_stall(ep);
1278 }
1279
1280 dwc2_udc_ep0_zlp(dev);
1281 return 0;
1282 }
1283
1284 return 1;
1285 }
1286
1287 /*
1288 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1289 */
dwc2_ep0_setup(struct dwc2_udc * dev)1290 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1291 {
1292 struct dwc2_ep *ep = &dev->ep[0];
1293 int i;
1294 u8 ep_num;
1295
1296 /* Nuke all previous transfers */
1297 nuke(ep, -EPROTO);
1298
1299 /* read control req from fifo (8 bytes) */
1300 dwc2_fifo_read(ep, usb_ctrl, 8);
1301
1302 debug_cond(DEBUG_SETUP != 0,
1303 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1304 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1305 __func__, usb_ctrl->bRequestType,
1306 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1307 usb_ctrl->bRequest,
1308 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1309
1310 #ifdef DEBUG
1311 {
1312 int i, len = sizeof(*usb_ctrl);
1313 char *p = (char *)usb_ctrl;
1314
1315 printf("pkt = ");
1316 for (i = 0; i < len; i++) {
1317 printf("%02x", ((u8 *)p)[i]);
1318 if ((i & 7) == 7)
1319 printf(" ");
1320 }
1321 printf("\n");
1322 }
1323 #endif
1324
1325 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1326 usb_ctrl->wLength != 1) {
1327 debug_cond(DEBUG_SETUP != 0,
1328 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1329 __func__);
1330 debug_cond(DEBUG_SETUP != 0,
1331 "wLength = %d, setup returned\n",
1332 usb_ctrl->wLength);
1333
1334 dwc2_udc_ep0_set_stall(ep);
1335 dev->ep0state = WAIT_FOR_SETUP;
1336
1337 return;
1338 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1339 usb_ctrl->wLength != 0) {
1340 /* Bulk-Only *mass storge reset of class-specific request */
1341 debug_cond(DEBUG_SETUP != 0,
1342 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1343 __func__, usb_ctrl->wLength);
1344
1345 dwc2_udc_ep0_set_stall(ep);
1346 dev->ep0state = WAIT_FOR_SETUP;
1347
1348 return;
1349 }
1350
1351 /* Set direction of EP0 */
1352 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1353 ep->bEndpointAddress |= USB_DIR_IN;
1354 } else {
1355 ep->bEndpointAddress &= ~USB_DIR_IN;
1356 }
1357 /* cope with automagic for some standard requests. */
1358 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1359 == USB_TYPE_STANDARD;
1360
1361 dev->req_pending = 1;
1362
1363 /* Handle some SETUP packets ourselves */
1364 if (dev->req_std) {
1365 switch (usb_ctrl->bRequest) {
1366 case USB_REQ_SET_ADDRESS:
1367 debug_cond(DEBUG_SETUP != 0,
1368 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1369 __func__, usb_ctrl->wValue);
1370 if (usb_ctrl->bRequestType
1371 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1372 break;
1373 dev->connected = 1;
1374 udc_set_address(dev, usb_ctrl->wValue);
1375 return;
1376
1377 case USB_REQ_SET_CONFIGURATION:
1378 debug_cond(DEBUG_SETUP != 0,
1379 "=====================================\n");
1380 debug_cond(DEBUG_SETUP != 0,
1381 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1382 __func__, usb_ctrl->wValue);
1383
1384 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1385 reset_available = 1;
1386
1387 break;
1388
1389 case USB_REQ_GET_DESCRIPTOR:
1390 debug_cond(DEBUG_SETUP != 0,
1391 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1392 __func__);
1393 break;
1394
1395 case USB_REQ_SET_INTERFACE:
1396 debug_cond(DEBUG_SETUP != 0,
1397 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1398 __func__, usb_ctrl->wValue);
1399
1400 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1401 reset_available = 1;
1402
1403 break;
1404
1405 case USB_REQ_GET_CONFIGURATION:
1406 debug_cond(DEBUG_SETUP != 0,
1407 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1408 __func__);
1409 break;
1410
1411 case USB_REQ_GET_STATUS:
1412 if (!dwc2_udc_get_status(dev, usb_ctrl))
1413 return;
1414
1415 break;
1416
1417 case USB_REQ_CLEAR_FEATURE:
1418 ep_num = usb_ctrl->wIndex & 0x7f;
1419
1420 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1421 return;
1422
1423 break;
1424
1425 case USB_REQ_SET_FEATURE:
1426 ep_num = usb_ctrl->wIndex & 0x7f;
1427
1428 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1429 return;
1430
1431 break;
1432
1433 default:
1434 debug_cond(DEBUG_SETUP != 0,
1435 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1436 "happened.\n", __func__, usb_ctrl->bRequest);
1437 break;
1438 }
1439 }
1440
1441
1442 if (likely(dev->driver)) {
1443 /* device-2-host (IN) or no data setup command,
1444 * process immediately */
1445 debug_cond(DEBUG_SETUP != 0,
1446 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1447 __func__);
1448
1449 spin_unlock(&dev->lock);
1450 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1451 spin_lock(&dev->lock);
1452
1453 if (i < 0) {
1454 /* setup processing failed, force stall */
1455 dwc2_udc_ep0_set_stall(ep);
1456 dev->ep0state = WAIT_FOR_SETUP;
1457
1458 debug_cond(DEBUG_SETUP != 0,
1459 "\tdev->driver->setup failed (%d),"
1460 " bRequest = %d\n",
1461 i, usb_ctrl->bRequest);
1462
1463
1464 } else if (dev->req_pending) {
1465 dev->req_pending = 0;
1466 debug_cond(DEBUG_SETUP != 0,
1467 "\tdev->req_pending...\n");
1468 }
1469
1470 debug_cond(DEBUG_SETUP != 0,
1471 "\tep0state = %s\n", state_names[dev->ep0state]);
1472
1473 }
1474 }
1475
1476 /*
1477 * handle ep0 interrupt
1478 */
dwc2_handle_ep0(struct dwc2_udc * dev)1479 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1480 {
1481 if (dev->ep0state == WAIT_FOR_SETUP) {
1482 debug_cond(DEBUG_OUT_EP != 0,
1483 "%s: WAIT_FOR_SETUP\n", __func__);
1484 dwc2_ep0_setup(dev);
1485
1486 } else {
1487 debug_cond(DEBUG_OUT_EP != 0,
1488 "%s: strange state!!(state = %s)\n",
1489 __func__, state_names[dev->ep0state]);
1490 }
1491 }
1492
dwc2_ep0_kick(struct dwc2_udc * dev,struct dwc2_ep * ep)1493 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1494 {
1495 debug_cond(DEBUG_EP0 != 0,
1496 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1497 if (ep_is_in(ep)) {
1498 dev->ep0state = DATA_STATE_XMIT;
1499 dwc2_ep0_write(dev);
1500
1501 } else {
1502 dev->ep0state = DATA_STATE_RECV;
1503 dwc2_ep0_read(dev);
1504 }
1505 }
1506