1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Designware DWC2 on-chip full/high speed USB device controllers 3*4882a593Smuzhiyun * Copyright (C) 2005 for Samsung Electronics 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DWC2_UDC_OTG_PRIV__ 9*4882a593Smuzhiyun #define __DWC2_UDC_OTG_PRIV__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/errno.h> 12*4882a593Smuzhiyun #include <linux/sizes.h> 13*4882a593Smuzhiyun #include <linux/usb/ch9.h> 14*4882a593Smuzhiyun #include <linux/usb/gadget.h> 15*4882a593Smuzhiyun #include <linux/list.h> 16*4882a593Smuzhiyun #include <usb/dwc2_udc.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/ 19*4882a593Smuzhiyun /* DMA bounce buffer size, 16K is enough even for mass storage */ 20*4882a593Smuzhiyun #define DMA_BUFFER_SIZE (16*SZ_1K) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define EP0_FIFO_SIZE 64 23*4882a593Smuzhiyun #define EP_FIFO_SIZE 512 24*4882a593Smuzhiyun #define EP_FIFO_SIZE2 1024 25*4882a593Smuzhiyun /* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */ 26*4882a593Smuzhiyun #define DWC2_MAX_ENDPOINTS 4 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define WAIT_FOR_SETUP 0 29*4882a593Smuzhiyun #define DATA_STATE_XMIT 1 30*4882a593Smuzhiyun #define DATA_STATE_NEED_ZLP 2 31*4882a593Smuzhiyun #define WAIT_FOR_OUT_STATUS 3 32*4882a593Smuzhiyun #define DATA_STATE_RECV 4 33*4882a593Smuzhiyun #define WAIT_FOR_COMPLETE 5 34*4882a593Smuzhiyun #define WAIT_FOR_OUT_COMPLETE 6 35*4882a593Smuzhiyun #define WAIT_FOR_IN_COMPLETE 7 36*4882a593Smuzhiyun #define WAIT_FOR_NULL_COMPLETE 8 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define TEST_J_SEL 0x1 39*4882a593Smuzhiyun #define TEST_K_SEL 0x2 40*4882a593Smuzhiyun #define TEST_SE0_NAK_SEL 0x3 41*4882a593Smuzhiyun #define TEST_PACKET_SEL 0x4 42*4882a593Smuzhiyun #define TEST_FORCE_ENABLE_SEL 0x5 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* ************************************************************************* */ 45*4882a593Smuzhiyun /* IO 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun enum ep_type { 49*4882a593Smuzhiyun ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct dwc2_ep { 53*4882a593Smuzhiyun struct usb_ep ep; 54*4882a593Smuzhiyun struct dwc2_udc *dev; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun const struct usb_endpoint_descriptor *desc; 57*4882a593Smuzhiyun struct list_head queue; 58*4882a593Smuzhiyun unsigned long pio_irqs; 59*4882a593Smuzhiyun int len; 60*4882a593Smuzhiyun void *dma_buf; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun u8 stopped; 63*4882a593Smuzhiyun u8 bEndpointAddress; 64*4882a593Smuzhiyun u8 bmAttributes; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun enum ep_type ep_type; 67*4882a593Smuzhiyun int fifo_num; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct dwc2_request { 71*4882a593Smuzhiyun struct usb_request req; 72*4882a593Smuzhiyun struct list_head queue; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct dwc2_udc { 76*4882a593Smuzhiyun struct usb_gadget gadget; 77*4882a593Smuzhiyun struct usb_gadget_driver *driver; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct dwc2_plat_otg_data *pdata; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun int ep0state; 82*4882a593Smuzhiyun struct dwc2_ep ep[DWC2_MAX_ENDPOINTS]; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun unsigned char usb_address; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun unsigned req_pending:1, req_std:1; 87*4882a593Smuzhiyun unsigned connected:1; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN) 91*4882a593Smuzhiyun #define ep_index(EP) ((EP)->bEndpointAddress&0xF) 92*4882a593Smuzhiyun #define ep_maxpacket(EP) ((EP)->ep.maxpacket) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun void otg_phy_init(struct dwc2_udc *dev); 95*4882a593Smuzhiyun void otg_phy_off(struct dwc2_udc *dev); 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* __DWC2_UDC_OTG_PRIV__ */ 98