1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel PXA25x on-chip full speed USB device controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
6*4882a593Smuzhiyun * Copyright (C) 2003 David Brownell
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __LINUX_USB_GADGET_PXA25X_H
10*4882a593Smuzhiyun #define __LINUX_USB_GADGET_PXA25X_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/types.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* pxa25x has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
17*4882a593Smuzhiyun #define UFNRH_SIR (1 << 7) /* SOF interrupt request */
18*4882a593Smuzhiyun #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */
19*4882a593Smuzhiyun #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */
20*4882a593Smuzhiyun #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */
21*4882a593Smuzhiyun #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* pxa255 has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
24*4882a593Smuzhiyun #define UDCCFR UDC_RES2 /* UDC Control Function Register */
25*4882a593Smuzhiyun #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */
26*4882a593Smuzhiyun #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* latest pxa255 errata define new "must be one" bits in UDCCFR */
29*4882a593Smuzhiyun #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN|UDCCFR_ACM))
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct pxa25x_udc;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct pxa25x_ep {
36*4882a593Smuzhiyun struct usb_ep ep;
37*4882a593Smuzhiyun struct pxa25x_udc *dev;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct list_head queue;
40*4882a593Smuzhiyun unsigned long pio_irqs;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun unsigned short fifo_size;
43*4882a593Smuzhiyun u8 bEndpointAddress;
44*4882a593Smuzhiyun u8 bmAttributes;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun unsigned stopped : 1;
47*4882a593Smuzhiyun unsigned dma_fixup : 1;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* UDCCS = UDC Control/Status for this EP
50*4882a593Smuzhiyun * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
51*4882a593Smuzhiyun * UDDR = UDC Endpoint Data Register (the fifo)
52*4882a593Smuzhiyun * DRCM = DMA Request Channel Map
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun u32 regoff_udccs;
55*4882a593Smuzhiyun u32 regoff_ubcr;
56*4882a593Smuzhiyun u32 regoff_uddr;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun struct pxa25x_request {
60*4882a593Smuzhiyun struct usb_request req;
61*4882a593Smuzhiyun struct list_head queue;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun enum ep0_state {
65*4882a593Smuzhiyun EP0_IDLE,
66*4882a593Smuzhiyun EP0_IN_DATA_PHASE,
67*4882a593Smuzhiyun EP0_OUT_DATA_PHASE,
68*4882a593Smuzhiyun EP0_END_XFER,
69*4882a593Smuzhiyun EP0_STALL,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define EP0_FIFO_SIZE ((unsigned)16)
73*4882a593Smuzhiyun #define BULK_FIFO_SIZE ((unsigned)64)
74*4882a593Smuzhiyun #define ISO_FIFO_SIZE ((unsigned)256)
75*4882a593Smuzhiyun #define INT_FIFO_SIZE ((unsigned)8)
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct udc_stats {
78*4882a593Smuzhiyun struct ep0stats {
79*4882a593Smuzhiyun unsigned long ops;
80*4882a593Smuzhiyun unsigned long bytes;
81*4882a593Smuzhiyun } read, write;
82*4882a593Smuzhiyun unsigned long irqs;
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #ifdef CONFIG_USB_PXA25X_SMALL
86*4882a593Smuzhiyun /* when memory's tight, SMALL config saves code+data. */
87*4882a593Smuzhiyun #define PXA_UDC_NUM_ENDPOINTS 3
88*4882a593Smuzhiyun #endif
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #ifndef PXA_UDC_NUM_ENDPOINTS
91*4882a593Smuzhiyun #define PXA_UDC_NUM_ENDPOINTS 16
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun struct pxa25x_udc {
95*4882a593Smuzhiyun struct usb_gadget gadget;
96*4882a593Smuzhiyun struct usb_gadget_driver *driver;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun enum ep0_state ep0state;
99*4882a593Smuzhiyun struct udc_stats stats;
100*4882a593Smuzhiyun unsigned got_irq : 1,
101*4882a593Smuzhiyun vbus : 1,
102*4882a593Smuzhiyun pullup : 1,
103*4882a593Smuzhiyun has_cfr : 1,
104*4882a593Smuzhiyun req_pending : 1,
105*4882a593Smuzhiyun req_std : 1,
106*4882a593Smuzhiyun req_config : 1,
107*4882a593Smuzhiyun suspended : 1,
108*4882a593Smuzhiyun active : 1;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200))
111*4882a593Smuzhiyun struct timer_list timer;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun struct device *dev;
114*4882a593Smuzhiyun struct clk *clk;
115*4882a593Smuzhiyun struct pxa2xx_udc_mach_info *mach;
116*4882a593Smuzhiyun struct usb_phy *transceiver;
117*4882a593Smuzhiyun u64 dma_mask;
118*4882a593Smuzhiyun struct pxa25x_ep ep [PXA_UDC_NUM_ENDPOINTS];
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun #ifdef CONFIG_USB_GADGET_DEBUG_FS
121*4882a593Smuzhiyun struct dentry *debugfs_udc;
122*4882a593Smuzhiyun #endif
123*4882a593Smuzhiyun void __iomem *regs;
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun #define to_pxa25x(g) (container_of((g), struct pxa25x_udc, gadget))
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #ifdef CONFIG_ARCH_LUBBOCK
130*4882a593Smuzhiyun #include <mach/lubbock.h>
131*4882a593Smuzhiyun /* lubbock can also report usb connect/disconnect irqs */
132*4882a593Smuzhiyun #endif
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun static struct pxa25x_udc *the_controller;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /*
139*4882a593Smuzhiyun * Debugging support vanishes in non-debug builds. DBG_NORMAL should be
140*4882a593Smuzhiyun * mostly silent during normal use/testing, with no timing side-effects.
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun #define DBG_NORMAL 1 /* error paths, device state transitions */
143*4882a593Smuzhiyun #define DBG_VERBOSE 2 /* add some success path trace info */
144*4882a593Smuzhiyun #define DBG_NOISY 3 /* ... even more: request level */
145*4882a593Smuzhiyun #define DBG_VERY_NOISY 4 /* ... even more: packet level */
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun #define DMSG(stuff...) pr_debug("udc: " stuff)
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun #ifdef DEBUG
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const char *state_name[] = {
152*4882a593Smuzhiyun "EP0_IDLE",
153*4882a593Smuzhiyun "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
154*4882a593Smuzhiyun "EP0_END_XFER", "EP0_STALL"
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun #ifdef VERBOSE_DEBUG
158*4882a593Smuzhiyun # define UDC_DEBUG DBG_VERBOSE
159*4882a593Smuzhiyun #else
160*4882a593Smuzhiyun # define UDC_DEBUG DBG_NORMAL
161*4882a593Smuzhiyun #endif
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static void __maybe_unused
dump_udccr(const char * label)164*4882a593Smuzhiyun dump_udccr(const char *label)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun u32 udccr = UDCCR;
167*4882a593Smuzhiyun DMSG("%s %02X =%s%s%s%s%s%s%s%s\n",
168*4882a593Smuzhiyun label, udccr,
169*4882a593Smuzhiyun (udccr & UDCCR_REM) ? " rem" : "",
170*4882a593Smuzhiyun (udccr & UDCCR_RSTIR) ? " rstir" : "",
171*4882a593Smuzhiyun (udccr & UDCCR_SRM) ? " srm" : "",
172*4882a593Smuzhiyun (udccr & UDCCR_SUSIR) ? " susir" : "",
173*4882a593Smuzhiyun (udccr & UDCCR_RESIR) ? " resir" : "",
174*4882a593Smuzhiyun (udccr & UDCCR_RSM) ? " rsm" : "",
175*4882a593Smuzhiyun (udccr & UDCCR_UDA) ? " uda" : "",
176*4882a593Smuzhiyun (udccr & UDCCR_UDE) ? " ude" : "");
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static void __maybe_unused
dump_udccs0(const char * label)180*4882a593Smuzhiyun dump_udccs0(const char *label)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun u32 udccs0 = UDCCS0;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun DMSG("%s %s %02X =%s%s%s%s%s%s%s%s\n",
185*4882a593Smuzhiyun label, state_name[the_controller->ep0state], udccs0,
186*4882a593Smuzhiyun (udccs0 & UDCCS0_SA) ? " sa" : "",
187*4882a593Smuzhiyun (udccs0 & UDCCS0_RNE) ? " rne" : "",
188*4882a593Smuzhiyun (udccs0 & UDCCS0_FST) ? " fst" : "",
189*4882a593Smuzhiyun (udccs0 & UDCCS0_SST) ? " sst" : "",
190*4882a593Smuzhiyun (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
191*4882a593Smuzhiyun (udccs0 & UDCCS0_FTF) ? " ftf" : "",
192*4882a593Smuzhiyun (udccs0 & UDCCS0_IPR) ? " ipr" : "",
193*4882a593Smuzhiyun (udccs0 & UDCCS0_OPR) ? " opr" : "");
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun static void __maybe_unused
dump_state(struct pxa25x_udc * dev)199*4882a593Smuzhiyun dump_state(struct pxa25x_udc *dev)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun u32 tmp;
202*4882a593Smuzhiyun unsigned i;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun DMSG("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
205*4882a593Smuzhiyun state_name[dev->ep0state],
206*4882a593Smuzhiyun UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
207*4882a593Smuzhiyun dump_udccr("udccr");
208*4882a593Smuzhiyun if (dev->has_cfr) {
209*4882a593Smuzhiyun tmp = UDCCFR;
210*4882a593Smuzhiyun DMSG("udccfr %02X =%s%s\n", tmp,
211*4882a593Smuzhiyun (tmp & UDCCFR_AREN) ? " aren" : "",
212*4882a593Smuzhiyun (tmp & UDCCFR_ACM) ? " acm" : "");
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (!dev->driver) {
216*4882a593Smuzhiyun DMSG("no gadget driver bound\n");
217*4882a593Smuzhiyun return;
218*4882a593Smuzhiyun } else
219*4882a593Smuzhiyun DMSG("ep0 driver '%s'\n", dev->driver->driver.name);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun dump_udccs0 ("udccs0");
222*4882a593Smuzhiyun DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n",
223*4882a593Smuzhiyun dev->stats.write.bytes, dev->stats.write.ops,
224*4882a593Smuzhiyun dev->stats.read.bytes, dev->stats.read.ops);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
227*4882a593Smuzhiyun if (dev->ep[i].ep.desc == NULL)
228*4882a593Smuzhiyun continue;
229*4882a593Smuzhiyun DMSG ("udccs%d = %02x\n", i, udc_ep_get_UDCCS(&dev->ep[i]));
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun #else
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun #define dump_udccr(x) do{}while(0)
236*4882a593Smuzhiyun #define dump_udccs0(x) do{}while(0)
237*4882a593Smuzhiyun #define dump_state(x) do{}while(0)
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun #define UDC_DEBUG ((unsigned)0)
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun #endif
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun #define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0)
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun #define ERR(stuff...) pr_err("udc: " stuff)
246*4882a593Smuzhiyun #define WARNING(stuff...) pr_warn("udc: " stuff)
247*4882a593Smuzhiyun #define INFO(stuff...) pr_info("udc: " stuff)
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun #endif /* __LINUX_USB_GADGET_PXA25X_H */
251