| /OK3568_Linux_fs/u-boot/drivers/clk/ |
| H A D | clk_zynq.c | 102 static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) in zynq_clk_get_cpu_pll() argument
104 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_cpu_pll()
117 static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) in zynq_clk_get_peripheral_pll() argument
119 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_peripheral_pll()
134 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local
136 clk_ctrl = readl(zynq_clk_get_register(id)); in zynq_clk_get_pll_rate()
138 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; in zynq_clk_get_pll_rate()
139 pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; in zynq_clk_get_pll_rate()
143 bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; in zynq_clk_get_pll_rate()
147 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynq_clk_get_pll_rate()
[all …]
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| H A D | clk_zynqmp.c | 235 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl) in zynqmp_clk_get_cpu_pll() argument
237 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_cpu_pll()
251 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl) in zynqmp_clk_get_ddr_pll() argument
253 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_ddr_pll()
265 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl) in zynqmp_clk_get_peripheral_pll() argument
267 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_peripheral_pll()
281 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl, in zynqmp_clk_get_pll_src() argument
288 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >> in zynqmp_clk_get_pll_src()
291 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >> in zynqmp_clk_get_pll_src()
312 u32 clk_ctrl, reset, mul; in zynqmp_clk_get_pll_rate() local
[all …]
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| /OK3568_Linux_fs/kernel/arch/mips/ath79/ |
| H A D | clock.c | 238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
307 clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_clocks_init()
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
312 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) in ar934x_clocks_init()
314 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
322 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_clocks_init()
324 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
332 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) in ar934x_clocks_init()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_vbif.h | 19 u32 clk_ctrl; member
25 u32 clk_ctrl; member
40 u32 clk_ctrl; member
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| H A D | dpu_hw_top.c | 92 enum dpu_clk_ctrl_type clk_ctrl, bool enable) in dpu_hw_setup_clk_force_ctrl() argument
104 if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX) in dpu_hw_setup_clk_force_ctrl()
107 reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; in dpu_hw_setup_clk_force_ctrl()
108 bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off; in dpu_hw_setup_clk_force_ctrl()
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| H A D | dpu_vbif.c | 191 forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); in dpu_vbif_set_ot_limit()
204 mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); in dpu_vbif_set_ot_limit()
242 forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); in dpu_vbif_set_qos_remap()
253 mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); in dpu_vbif_set_qos_remap()
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| H A D | dpu_hw_top.h | 103 enum dpu_clk_ctrl_type clk_ctrl, bool enable);
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| H A D | dpu_hw_catalog.h | 484 enum dpu_clk_ctrl_type clk_ctrl; member
617 enum dpu_clk_ctrl_type clk_ctrl; member
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| H A D | dpu_plane.c | 469 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; in _dpu_plane_set_ot_limit()
487 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; in _dpu_plane_set_qos_remap()
496 qos_params.clk_ctrl); in _dpu_plane_set_qos_remap()
1469 (u32 *) &cfg->clk_ctrl); in _dpu_plane_init_debugfs()
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| H A D | dpu_hw_catalog.c | 338 .clk_ctrl = _clkctrl \
591 .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
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| /OK3568_Linux_fs/kernel/include/linux/platform_data/ |
| H A D | net-cw1200.h | 21 int (*clk_ctrl)(const struct cw1200_platform_data_spi *pdata, member
38 int (*clk_ctrl)(const struct cw1200_platform_data_sdio *pdata, member
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/st/cw1200/ |
| H A D | cw1200_sdio.c | 191 if (pdata->clk_ctrl) in cw1200_sdio_off()
192 pdata->clk_ctrl(pdata, false); in cw1200_sdio_off()
220 if (pdata->clk_ctrl) { in cw1200_sdio_on()
221 if (pdata->clk_ctrl(pdata, true)) { in cw1200_sdio_on()
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| H A D | cw1200_spi.c | 288 if (pdata->clk_ctrl) in cw1200_spi_off()
289 pdata->clk_ctrl(pdata, false); in cw1200_spi_off()
317 if (pdata->clk_ctrl) { in cw1200_spi_on()
318 if (pdata->clk_ctrl(pdata, true)) { in cw1200_spi_on()
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| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | fsl_lsch3_speed.c | 33 struct ccsr_clk_ctrl __iomem *clk_ctrl = in get_sys_info() local
118 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27) in get_sys_info()
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| /OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/armada100/ |
| H A D | timer.c | 19 u32 clk_ctrl; /* Timer clk control reg */ member
112 writel(0x0, &armd1timers->clk_ctrl); in timer_init()
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| /OK3568_Linux_fs/kernel/drivers/clk/zynq/ |
| H A D | clkc.c | 176 const char *clk_name1, void __iomem *clk_ctrl, in zynq_clk_register_periph_clk() argument
193 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); in zynq_clk_register_periph_clk()
195 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, in zynq_clk_register_periph_clk()
199 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); in zynq_clk_register_periph_clk()
202 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); in zynq_clk_register_periph_clk()
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| /OK3568_Linux_fs/u-boot/drivers/spi/ |
| H A D | ti_qspi.c | 85 u32 clk_ctrl; member
133 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, in ti_spi_set_speed()
134 &priv->base->clk_ctrl); in ti_spi_set_speed()
136 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_spi_set_speed()
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| /OK3568_Linux_fs/kernel/sound/soc/codecs/ |
| H A D | pcm186x.c | 362 u8 clk_ctrl = 0; in pcm186x_set_fmt() local
374 clk_ctrl |= PCM186X_CLK_CTRL_MST_MODE; in pcm186x_set_fmt()
418 PCM186X_CLK_CTRL_MST_MODE, clk_ctrl); in pcm186x_set_fmt()
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| /OK3568_Linux_fs/kernel/drivers/clk/bcm/ |
| H A D | clk-iproc.h | 217 const struct iproc_clk_ctrl *clk_ctrl,
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| H A D | clk-iproc-pll.c | 729 const struct iproc_clk_ctrl *clk_ctrl, in iproc_pll_clk_setup() argument
741 if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) in iproc_pll_clk_setup()
825 iclk->ctrl = &clk_ctrl[i]; in iproc_pll_clk_setup()
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| /OK3568_Linux_fs/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-typec.c | 786 u32 clk_ctrl; in tcphy_cfg_dp_pll() local
794 clk_ctrl = DP_PLL_DATA_RATE_HBR2; in tcphy_cfg_dp_pll()
800 clk_ctrl = DP_PLL_DATA_RATE_HBR; in tcphy_cfg_dp_pll()
807 clk_ctrl = DP_PLL_DATA_RATE_RBR; in tcphy_cfg_dp_pll()
814 clk_ctrl |= DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE; in tcphy_cfg_dp_pll()
815 writel(clk_ctrl, tcphy->base + PHY_DP_CLK_CTL); in tcphy_cfg_dp_pll()
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| /OK3568_Linux_fs/kernel/drivers/mmc/host/ |
| H A D | sdhci-tegra.c | 363 u32 misc_ctrl, clk_ctrl, pad_ctrl; in tegra_sdhci_reset() local
373 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_reset()
380 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | in tegra_sdhci_reset()
395 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; in tegra_sdhci_reset()
398 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; in tegra_sdhci_reset()
401 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_reset()
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