235 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)  in zynqmp_clk_get_cpu_pll()  argument
237 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>  in zynqmp_clk_get_cpu_pll()
251 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)  in zynqmp_clk_get_ddr_pll()  argument
253 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>  in zynqmp_clk_get_ddr_pll()
265 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)  in zynqmp_clk_get_peripheral_pll()  argument
267 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>  in zynqmp_clk_get_peripheral_pll()
281 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,  in zynqmp_clk_get_pll_src()  argument
288 		src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>  in zynqmp_clk_get_pll_src()
291 		src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>  in zynqmp_clk_get_pll_src()
312 	u32 clk_ctrl, reset, mul;  in zynqmp_clk_get_pll_rate()  local
316 	ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);  in zynqmp_clk_get_pll_rate()
322 	if (clk_ctrl & PLLCTRL_BYPASS_MASK)  in zynqmp_clk_get_pll_rate()
323 		freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);  in zynqmp_clk_get_pll_rate()
325 		freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);  in zynqmp_clk_get_pll_rate()
327 	reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;  in zynqmp_clk_get_pll_rate()
328 	if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))  in zynqmp_clk_get_pll_rate()
331 	mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;  in zynqmp_clk_get_pll_rate()
335 	if (clk_ctrl & (1 << 16))  in zynqmp_clk_get_pll_rate()
344 	u32 clk_ctrl, div;  in zynqmp_clk_get_cpu_rate()  local
349 	ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);  in zynqmp_clk_get_cpu_rate()
355 	div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_get_cpu_rate()
357 	pll = zynqmp_clk_get_cpu_pll(clk_ctrl);  in zynqmp_clk_get_cpu_rate()
367 	u32 clk_ctrl, div;  in zynqmp_clk_get_ddr_rate()  local
372 	ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);  in zynqmp_clk_get_ddr_rate()
378 	div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_get_ddr_rate()
380 	pll = zynqmp_clk_get_ddr_pll(clk_ctrl);  in zynqmp_clk_get_ddr_rate()
392 	u32 clk_ctrl, div0;  in zynqmp_clk_get_peripheral_rate()  local
397 	ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);  in zynqmp_clk_get_peripheral_rate()
403 	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_get_peripheral_rate()
408 		div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;  in zynqmp_clk_get_peripheral_rate()
413 	pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);  in zynqmp_clk_get_peripheral_rate()
454 	u32 clk_ctrl, div0 = 0, div1 = 0;  in zynqmp_clk_set_peripheral_rate()  local
461 	ret = zynqmp_mmio_read(reg, &clk_ctrl);  in zynqmp_clk_set_peripheral_rate()
467 	pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);  in zynqmp_clk_set_peripheral_rate()
472 	clk_ctrl &= ~CLK_CTRL_DIV0_MASK;  in zynqmp_clk_set_peripheral_rate()
474 		clk_ctrl &= ~CLK_CTRL_DIV1_MASK;  in zynqmp_clk_set_peripheral_rate()
477 		clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;  in zynqmp_clk_set_peripheral_rate()
484 	clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_set_peripheral_rate()
489 	ret = zynqmp_mmio_write(reg, mask, clk_ctrl);  in zynqmp_clk_set_peripheral_rate()