1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) ST-Ericsson SA 2011 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Dmitry Tarnyagin <dmitry.tarnyagin@stericsson.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef CW1200_PLAT_H_INCLUDED 9*4882a593Smuzhiyun #define CW1200_PLAT_H_INCLUDED 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct cw1200_platform_data_spi { 12*4882a593Smuzhiyun u8 spi_bits_per_word; /* REQUIRED */ 13*4882a593Smuzhiyun u16 ref_clk; /* REQUIRED (in KHz) */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* All others are optional */ 16*4882a593Smuzhiyun bool have_5ghz; 17*4882a593Smuzhiyun int reset; /* GPIO to RSTn signal (0 disables) */ 18*4882a593Smuzhiyun int powerup; /* GPIO to POWERUP signal (0 disables) */ 19*4882a593Smuzhiyun int (*power_ctrl)(const struct cw1200_platform_data_spi *pdata, 20*4882a593Smuzhiyun bool enable); /* Control 3v3 / 1v8 supply */ 21*4882a593Smuzhiyun int (*clk_ctrl)(const struct cw1200_platform_data_spi *pdata, 22*4882a593Smuzhiyun bool enable); /* Control CLK32K */ 23*4882a593Smuzhiyun const u8 *macaddr; /* if NULL, use cw1200_mac_template module parameter */ 24*4882a593Smuzhiyun const char *sdd_file; /* if NULL, will use default for detected hw type */ 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct cw1200_platform_data_sdio { 28*4882a593Smuzhiyun u16 ref_clk; /* REQUIRED (in KHz) */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* All others are optional */ 31*4882a593Smuzhiyun bool have_5ghz; 32*4882a593Smuzhiyun bool no_nptb; /* SDIO hardware does not support non-power-of-2-blocksizes */ 33*4882a593Smuzhiyun int reset; /* GPIO to RSTn signal (0 disables) */ 34*4882a593Smuzhiyun int powerup; /* GPIO to POWERUP signal (0 disables) */ 35*4882a593Smuzhiyun int irq; /* IRQ line or 0 to use SDIO IRQ */ 36*4882a593Smuzhiyun int (*power_ctrl)(const struct cw1200_platform_data_sdio *pdata, 37*4882a593Smuzhiyun bool enable); /* Control 3v3 / 1v8 supply */ 38*4882a593Smuzhiyun int (*clk_ctrl)(const struct cw1200_platform_data_sdio *pdata, 39*4882a593Smuzhiyun bool enable); /* Control CLK32K */ 40*4882a593Smuzhiyun const u8 *macaddr; /* if NULL, use cw1200_mac_template module parameter */ 41*4882a593Smuzhiyun const char *sdd_file; /* if NULL, will use default for detected hw type */ 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* An example of SPI support in your board setup file: 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun static struct cw1200_platform_data_spi cw1200_platform_data = { 48*4882a593Smuzhiyun .ref_clk = 38400, 49*4882a593Smuzhiyun .spi_bits_per_word = 16, 50*4882a593Smuzhiyun .reset = GPIO_RF_RESET, 51*4882a593Smuzhiyun .powerup = GPIO_RF_POWERUP, 52*4882a593Smuzhiyun .macaddr = wifi_mac_addr, 53*4882a593Smuzhiyun .sdd_file = "sdd_sagrad_1091_1098.bin", 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun static struct spi_board_info myboard_spi_devices[] __initdata = { 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun .modalias = "cw1200_wlan_spi", 58*4882a593Smuzhiyun .max_speed_hz = 52000000, 59*4882a593Smuzhiyun .bus_num = 0, 60*4882a593Smuzhiyun .irq = WIFI_IRQ, 61*4882a593Smuzhiyun .platform_data = &cw1200_platform_data, 62*4882a593Smuzhiyun .chip_select = 0, 63*4882a593Smuzhiyun }, 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* An example of SDIO support in your board setup file: 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun static struct cw1200_platform_data_sdio my_cw1200_platform_data = { 71*4882a593Smuzhiyun .ref_clk = 38400, 72*4882a593Smuzhiyun .have_5ghz = false, 73*4882a593Smuzhiyun .sdd_file = "sdd_myplatform.bin", 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun cw1200_sdio_set_platform_data(&my_cw1200_platform_data); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun void __init cw1200_sdio_set_platform_data(struct cw1200_platform_data_sdio *pdata); 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* CW1200_PLAT_H_INCLUDED */ 82