102 static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl)  in zynq_clk_get_cpu_pll()  argument
104 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;  in zynq_clk_get_cpu_pll()
117 static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl)  in zynq_clk_get_peripheral_pll()  argument
119 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;  in zynq_clk_get_peripheral_pll()
134 	u32 clk_ctrl, reset, pwrdwn, mul, bypass;  in zynq_clk_get_pll_rate()  local
136 	clk_ctrl = readl(zynq_clk_get_register(id));  in zynq_clk_get_pll_rate()
138 	reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;  in zynq_clk_get_pll_rate()
139 	pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT;  in zynq_clk_get_pll_rate()
143 	bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK;  in zynq_clk_get_pll_rate()
147 		mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;  in zynq_clk_get_pll_rate()
155 	u32 clk_ctrl, srcsel;  in zynq_clk_get_gem_rclk()  local
158 		clk_ctrl = readl(&slcr_base->gem0_rclk_ctrl);  in zynq_clk_get_gem_rclk()
160 		clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl);  in zynq_clk_get_gem_rclk()
162 	srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;  in zynq_clk_get_gem_rclk()
172 	u32 clk_621, clk_ctrl, div;  in zynq_clk_get_cpu_rate()  local
175 	clk_ctrl = readl(&slcr_base->arm_clk_ctrl);  in zynq_clk_get_cpu_rate()
177 	div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynq_clk_get_cpu_rate()
196 	pll = zynq_clk_get_cpu_pll(clk_ctrl);  in zynq_clk_get_cpu_rate()
204 	u32 clk_ctrl, div;  in zynq_clk_get_ddr2x_rate()  local
206 	clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);  in zynq_clk_get_ddr2x_rate()
208 	div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;  in zynq_clk_get_ddr2x_rate()
216 	u32 clk_ctrl, div;  in zynq_clk_get_ddr3x_rate()  local
218 	clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);  in zynq_clk_get_ddr3x_rate()
220 	div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;  in zynq_clk_get_ddr3x_rate()
228 	u32 clk_ctrl, div0, div1;  in zynq_clk_get_dci_rate()  local
230 	clk_ctrl = readl(&slcr_base->dci_clk_ctrl);  in zynq_clk_get_dci_rate()
232 	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynq_clk_get_dci_rate()
233 	div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;  in zynq_clk_get_dci_rate()
244 	u32 clk_ctrl, div0;  in zynq_clk_get_peripheral_rate()  local
247 	clk_ctrl = readl(zynq_clk_get_register(id));  in zynq_clk_get_peripheral_rate()
249 	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynq_clk_get_peripheral_rate()
255 		div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;  in zynq_clk_get_peripheral_rate()
261 	pll = zynq_clk_get_peripheral_pll(clk_ctrl);  in zynq_clk_get_peripheral_rate()
319 	u32 clk_ctrl, div0 = 0, div1 = 0;  in zynq_clk_set_peripheral_rate()  local
324 	clk_ctrl = readl(reg);  in zynq_clk_set_peripheral_rate()
326 	pll = zynq_clk_get_peripheral_pll(clk_ctrl);  in zynq_clk_set_peripheral_rate()
328 	clk_ctrl &= ~CLK_CTRL_DIV0_MASK;  in zynq_clk_set_peripheral_rate()
330 		clk_ctrl &= ~CLK_CTRL_DIV1_MASK;  in zynq_clk_set_peripheral_rate()
333 		clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;  in zynq_clk_set_peripheral_rate()
340 	clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;  in zynq_clk_set_peripheral_rate()
343 	writel(clk_ctrl, reg);  in zynq_clk_set_peripheral_rate()