xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/st/cw1200/cw1200_spi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Mac80211 SPI driver for ST-Ericsson CW1200 device
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2011, Sagrad Inc.
6*4882a593Smuzhiyun  * Author:  Solomon Peachy <speachy@sagrad.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Based on cw1200_sdio.c
9*4882a593Smuzhiyun  * Copyright (c) 2010, ST-Ericsson
10*4882a593Smuzhiyun  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/gpio.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/spinlock.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <net/mac80211.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/spi/spi.h>
21*4882a593Smuzhiyun #include <linux/device.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "cw1200.h"
24*4882a593Smuzhiyun #include "hwbus.h"
25*4882a593Smuzhiyun #include <linux/platform_data/net-cw1200.h>
26*4882a593Smuzhiyun #include "hwio.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun MODULE_AUTHOR("Solomon Peachy <speachy@sagrad.com>");
29*4882a593Smuzhiyun MODULE_DESCRIPTION("mac80211 ST-Ericsson CW1200 SPI driver");
30*4882a593Smuzhiyun MODULE_LICENSE("GPL");
31*4882a593Smuzhiyun MODULE_ALIAS("spi:cw1200_wlan_spi");
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* #define SPI_DEBUG */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun struct hwbus_priv {
36*4882a593Smuzhiyun 	struct spi_device	*func;
37*4882a593Smuzhiyun 	struct cw1200_common	*core;
38*4882a593Smuzhiyun 	const struct cw1200_platform_data_spi *pdata;
39*4882a593Smuzhiyun 	spinlock_t		lock; /* Serialize all bus operations */
40*4882a593Smuzhiyun 	wait_queue_head_t       wq;
41*4882a593Smuzhiyun 	int claimed;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define SDIO_TO_SPI_ADDR(addr) ((addr & 0x1f)>>2)
45*4882a593Smuzhiyun #define SET_WRITE 0x7FFF /* usage: and operation */
46*4882a593Smuzhiyun #define SET_READ 0x8000  /* usage: or operation */
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* Notes on byte ordering:
49*4882a593Smuzhiyun    LE:  B0 B1 B2 B3
50*4882a593Smuzhiyun    BE:  B3 B2 B1 B0
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun    Hardware expects 32-bit data to be written as 16-bit BE words:
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun    B1 B0 B3 B2
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun 
cw1200_spi_memcpy_fromio(struct hwbus_priv * self,unsigned int addr,void * dst,int count)57*4882a593Smuzhiyun static int cw1200_spi_memcpy_fromio(struct hwbus_priv *self,
58*4882a593Smuzhiyun 				     unsigned int addr,
59*4882a593Smuzhiyun 				     void *dst, int count)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	int ret, i;
62*4882a593Smuzhiyun 	u16 regaddr;
63*4882a593Smuzhiyun 	struct spi_message      m;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	struct spi_transfer     t_addr = {
66*4882a593Smuzhiyun 		.tx_buf         = &regaddr,
67*4882a593Smuzhiyun 		.len            = sizeof(regaddr),
68*4882a593Smuzhiyun 	};
69*4882a593Smuzhiyun 	struct spi_transfer     t_msg = {
70*4882a593Smuzhiyun 		.rx_buf         = dst,
71*4882a593Smuzhiyun 		.len            = count,
72*4882a593Smuzhiyun 	};
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	regaddr = (SDIO_TO_SPI_ADDR(addr))<<12;
75*4882a593Smuzhiyun 	regaddr |= SET_READ;
76*4882a593Smuzhiyun 	regaddr |= (count>>1);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #ifdef SPI_DEBUG
79*4882a593Smuzhiyun 	pr_info("READ : %04d from 0x%02x (%04x)\n", count, addr, regaddr);
80*4882a593Smuzhiyun #endif
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	/* Header is LE16 */
83*4882a593Smuzhiyun 	regaddr = cpu_to_le16(regaddr);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* We have to byteswap if the SPI bus is limited to 8b operation
86*4882a593Smuzhiyun 	   or we are running on a Big Endian system
87*4882a593Smuzhiyun 	*/
88*4882a593Smuzhiyun #if defined(__LITTLE_ENDIAN)
89*4882a593Smuzhiyun 	if (self->func->bits_per_word == 8)
90*4882a593Smuzhiyun #endif
91*4882a593Smuzhiyun 		regaddr = swab16(regaddr);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	spi_message_init(&m);
94*4882a593Smuzhiyun 	spi_message_add_tail(&t_addr, &m);
95*4882a593Smuzhiyun 	spi_message_add_tail(&t_msg, &m);
96*4882a593Smuzhiyun 	ret = spi_sync(self->func, &m);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #ifdef SPI_DEBUG
99*4882a593Smuzhiyun 	pr_info("READ : ");
100*4882a593Smuzhiyun 	for (i = 0; i < t_addr.len; i++)
101*4882a593Smuzhiyun 		printk("%02x ", ((u8 *)t_addr.tx_buf)[i]);
102*4882a593Smuzhiyun 	printk(" : ");
103*4882a593Smuzhiyun 	for (i = 0; i < t_msg.len; i++)
104*4882a593Smuzhiyun 		printk("%02x ", ((u8 *)t_msg.rx_buf)[i]);
105*4882a593Smuzhiyun 	printk("\n");
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	/* We have to byteswap if the SPI bus is limited to 8b operation
109*4882a593Smuzhiyun 	   or we are running on a Big Endian system
110*4882a593Smuzhiyun 	*/
111*4882a593Smuzhiyun #if defined(__LITTLE_ENDIAN)
112*4882a593Smuzhiyun 	if (self->func->bits_per_word == 8)
113*4882a593Smuzhiyun #endif
114*4882a593Smuzhiyun 	{
115*4882a593Smuzhiyun 		uint16_t *buf = (uint16_t *)dst;
116*4882a593Smuzhiyun 		for (i = 0; i < ((count + 1) >> 1); i++)
117*4882a593Smuzhiyun 			buf[i] = swab16(buf[i]);
118*4882a593Smuzhiyun 	}
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	return ret;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
cw1200_spi_memcpy_toio(struct hwbus_priv * self,unsigned int addr,const void * src,int count)123*4882a593Smuzhiyun static int cw1200_spi_memcpy_toio(struct hwbus_priv *self,
124*4882a593Smuzhiyun 				   unsigned int addr,
125*4882a593Smuzhiyun 				   const void *src, int count)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	int rval, i;
128*4882a593Smuzhiyun 	u16 regaddr;
129*4882a593Smuzhiyun 	struct spi_transfer     t_addr = {
130*4882a593Smuzhiyun 		.tx_buf         = &regaddr,
131*4882a593Smuzhiyun 		.len            = sizeof(regaddr),
132*4882a593Smuzhiyun 	};
133*4882a593Smuzhiyun 	struct spi_transfer     t_msg = {
134*4882a593Smuzhiyun 		.tx_buf         = src,
135*4882a593Smuzhiyun 		.len            = count,
136*4882a593Smuzhiyun 	};
137*4882a593Smuzhiyun 	struct spi_message      m;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	regaddr = (SDIO_TO_SPI_ADDR(addr))<<12;
140*4882a593Smuzhiyun 	regaddr &= SET_WRITE;
141*4882a593Smuzhiyun 	regaddr |= (count>>1);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #ifdef SPI_DEBUG
144*4882a593Smuzhiyun 	pr_info("WRITE: %04d  to  0x%02x (%04x)\n", count, addr, regaddr);
145*4882a593Smuzhiyun #endif
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/* Header is LE16 */
148*4882a593Smuzhiyun 	regaddr = cpu_to_le16(regaddr);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	/* We have to byteswap if the SPI bus is limited to 8b operation
151*4882a593Smuzhiyun 	   or we are running on a Big Endian system
152*4882a593Smuzhiyun 	*/
153*4882a593Smuzhiyun #if defined(__LITTLE_ENDIAN)
154*4882a593Smuzhiyun 	if (self->func->bits_per_word == 8)
155*4882a593Smuzhiyun #endif
156*4882a593Smuzhiyun 	{
157*4882a593Smuzhiyun 		uint16_t *buf = (uint16_t *)src;
158*4882a593Smuzhiyun 	        regaddr = swab16(regaddr);
159*4882a593Smuzhiyun 		for (i = 0; i < ((count + 1) >> 1); i++)
160*4882a593Smuzhiyun 			buf[i] = swab16(buf[i]);
161*4882a593Smuzhiyun 	}
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun #ifdef SPI_DEBUG
164*4882a593Smuzhiyun 	pr_info("WRITE: ");
165*4882a593Smuzhiyun 	for (i = 0; i < t_addr.len; i++)
166*4882a593Smuzhiyun 		printk("%02x ", ((u8 *)t_addr.tx_buf)[i]);
167*4882a593Smuzhiyun 	printk(" : ");
168*4882a593Smuzhiyun 	for (i = 0; i < t_msg.len; i++)
169*4882a593Smuzhiyun 		printk("%02x ", ((u8 *)t_msg.tx_buf)[i]);
170*4882a593Smuzhiyun 	printk("\n");
171*4882a593Smuzhiyun #endif
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	spi_message_init(&m);
174*4882a593Smuzhiyun 	spi_message_add_tail(&t_addr, &m);
175*4882a593Smuzhiyun 	spi_message_add_tail(&t_msg, &m);
176*4882a593Smuzhiyun 	rval = spi_sync(self->func, &m);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun #ifdef SPI_DEBUG
179*4882a593Smuzhiyun 	pr_info("WROTE: %d\n", m.actual_length);
180*4882a593Smuzhiyun #endif
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #if defined(__LITTLE_ENDIAN)
183*4882a593Smuzhiyun 	/* We have to byteswap if the SPI bus is limited to 8b operation */
184*4882a593Smuzhiyun 	if (self->func->bits_per_word == 8)
185*4882a593Smuzhiyun #endif
186*4882a593Smuzhiyun 	{
187*4882a593Smuzhiyun 		uint16_t *buf = (uint16_t *)src;
188*4882a593Smuzhiyun 		for (i = 0; i < ((count + 1) >> 1); i++)
189*4882a593Smuzhiyun 			buf[i] = swab16(buf[i]);
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 	return rval;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
cw1200_spi_lock(struct hwbus_priv * self)194*4882a593Smuzhiyun static void cw1200_spi_lock(struct hwbus_priv *self)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	unsigned long flags;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	DECLARE_WAITQUEUE(wait, current);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	might_sleep();
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	add_wait_queue(&self->wq, &wait);
203*4882a593Smuzhiyun 	spin_lock_irqsave(&self->lock, flags);
204*4882a593Smuzhiyun 	while (1) {
205*4882a593Smuzhiyun 		set_current_state(TASK_UNINTERRUPTIBLE);
206*4882a593Smuzhiyun 		if (!self->claimed)
207*4882a593Smuzhiyun 			break;
208*4882a593Smuzhiyun 		spin_unlock_irqrestore(&self->lock, flags);
209*4882a593Smuzhiyun 		schedule();
210*4882a593Smuzhiyun 		spin_lock_irqsave(&self->lock, flags);
211*4882a593Smuzhiyun 	}
212*4882a593Smuzhiyun 	set_current_state(TASK_RUNNING);
213*4882a593Smuzhiyun 	self->claimed = 1;
214*4882a593Smuzhiyun 	spin_unlock_irqrestore(&self->lock, flags);
215*4882a593Smuzhiyun 	remove_wait_queue(&self->wq, &wait);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	return;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
cw1200_spi_unlock(struct hwbus_priv * self)220*4882a593Smuzhiyun static void cw1200_spi_unlock(struct hwbus_priv *self)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	unsigned long flags;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	spin_lock_irqsave(&self->lock, flags);
225*4882a593Smuzhiyun 	self->claimed = 0;
226*4882a593Smuzhiyun 	spin_unlock_irqrestore(&self->lock, flags);
227*4882a593Smuzhiyun 	wake_up(&self->wq);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	return;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun 
cw1200_spi_irq_handler(int irq,void * dev_id)232*4882a593Smuzhiyun static irqreturn_t cw1200_spi_irq_handler(int irq, void *dev_id)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun 	struct hwbus_priv *self = dev_id;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	if (self->core) {
237*4882a593Smuzhiyun 		cw1200_spi_lock(self);
238*4882a593Smuzhiyun 		cw1200_irq_handler(self->core);
239*4882a593Smuzhiyun 		cw1200_spi_unlock(self);
240*4882a593Smuzhiyun 		return IRQ_HANDLED;
241*4882a593Smuzhiyun 	} else {
242*4882a593Smuzhiyun 		return IRQ_NONE;
243*4882a593Smuzhiyun 	}
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
cw1200_spi_irq_subscribe(struct hwbus_priv * self)246*4882a593Smuzhiyun static int cw1200_spi_irq_subscribe(struct hwbus_priv *self)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 	int ret;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	pr_debug("SW IRQ subscribe\n");
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	ret = request_threaded_irq(self->func->irq, NULL,
253*4882a593Smuzhiyun 				   cw1200_spi_irq_handler,
254*4882a593Smuzhiyun 				   IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
255*4882a593Smuzhiyun 				   "cw1200_wlan_irq", self);
256*4882a593Smuzhiyun 	if (WARN_ON(ret < 0))
257*4882a593Smuzhiyun 		goto exit;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	ret = enable_irq_wake(self->func->irq);
260*4882a593Smuzhiyun 	if (WARN_ON(ret))
261*4882a593Smuzhiyun 		goto free_irq;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	return 0;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun free_irq:
266*4882a593Smuzhiyun 	free_irq(self->func->irq, self);
267*4882a593Smuzhiyun exit:
268*4882a593Smuzhiyun 	return ret;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun 
cw1200_spi_irq_unsubscribe(struct hwbus_priv * self)271*4882a593Smuzhiyun static void cw1200_spi_irq_unsubscribe(struct hwbus_priv *self)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun 	pr_debug("SW IRQ unsubscribe\n");
274*4882a593Smuzhiyun 	disable_irq_wake(self->func->irq);
275*4882a593Smuzhiyun 	free_irq(self->func->irq, self);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun 
cw1200_spi_off(const struct cw1200_platform_data_spi * pdata)278*4882a593Smuzhiyun static int cw1200_spi_off(const struct cw1200_platform_data_spi *pdata)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun 	if (pdata->reset) {
281*4882a593Smuzhiyun 		gpio_set_value(pdata->reset, 0);
282*4882a593Smuzhiyun 		msleep(30); /* Min is 2 * CLK32K cycles */
283*4882a593Smuzhiyun 		gpio_free(pdata->reset);
284*4882a593Smuzhiyun 	}
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	if (pdata->power_ctrl)
287*4882a593Smuzhiyun 		pdata->power_ctrl(pdata, false);
288*4882a593Smuzhiyun 	if (pdata->clk_ctrl)
289*4882a593Smuzhiyun 		pdata->clk_ctrl(pdata, false);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	return 0;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
cw1200_spi_on(const struct cw1200_platform_data_spi * pdata)294*4882a593Smuzhiyun static int cw1200_spi_on(const struct cw1200_platform_data_spi *pdata)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun 	/* Ensure I/Os are pulled low */
297*4882a593Smuzhiyun 	if (pdata->reset) {
298*4882a593Smuzhiyun 		gpio_request(pdata->reset, "cw1200_wlan_reset");
299*4882a593Smuzhiyun 		gpio_direction_output(pdata->reset, 0);
300*4882a593Smuzhiyun 	}
301*4882a593Smuzhiyun 	if (pdata->powerup) {
302*4882a593Smuzhiyun 		gpio_request(pdata->powerup, "cw1200_wlan_powerup");
303*4882a593Smuzhiyun 		gpio_direction_output(pdata->powerup, 0);
304*4882a593Smuzhiyun 	}
305*4882a593Smuzhiyun 	if (pdata->reset || pdata->powerup)
306*4882a593Smuzhiyun 		msleep(10); /* Settle time? */
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	/* Enable 3v3 and 1v8 to hardware */
309*4882a593Smuzhiyun 	if (pdata->power_ctrl) {
310*4882a593Smuzhiyun 		if (pdata->power_ctrl(pdata, true)) {
311*4882a593Smuzhiyun 			pr_err("power_ctrl() failed!\n");
312*4882a593Smuzhiyun 			return -1;
313*4882a593Smuzhiyun 		}
314*4882a593Smuzhiyun 	}
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	/* Enable CLK32K */
317*4882a593Smuzhiyun 	if (pdata->clk_ctrl) {
318*4882a593Smuzhiyun 		if (pdata->clk_ctrl(pdata, true)) {
319*4882a593Smuzhiyun 			pr_err("clk_ctrl() failed!\n");
320*4882a593Smuzhiyun 			return -1;
321*4882a593Smuzhiyun 		}
322*4882a593Smuzhiyun 		msleep(10); /* Delay until clock is stable for 2 cycles */
323*4882a593Smuzhiyun 	}
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	/* Enable POWERUP signal */
326*4882a593Smuzhiyun 	if (pdata->powerup) {
327*4882a593Smuzhiyun 		gpio_set_value(pdata->powerup, 1);
328*4882a593Smuzhiyun 		msleep(250); /* or more..? */
329*4882a593Smuzhiyun 	}
330*4882a593Smuzhiyun 	/* Enable RSTn signal */
331*4882a593Smuzhiyun 	if (pdata->reset) {
332*4882a593Smuzhiyun 		gpio_set_value(pdata->reset, 1);
333*4882a593Smuzhiyun 		msleep(50); /* Or more..? */
334*4882a593Smuzhiyun 	}
335*4882a593Smuzhiyun 	return 0;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun 
cw1200_spi_align_size(struct hwbus_priv * self,size_t size)338*4882a593Smuzhiyun static size_t cw1200_spi_align_size(struct hwbus_priv *self, size_t size)
339*4882a593Smuzhiyun {
340*4882a593Smuzhiyun 	return size & 1 ? size + 1 : size;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun 
cw1200_spi_pm(struct hwbus_priv * self,bool suspend)343*4882a593Smuzhiyun static int cw1200_spi_pm(struct hwbus_priv *self, bool suspend)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun 	return irq_set_irq_wake(self->func->irq, suspend);
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun static const struct hwbus_ops cw1200_spi_hwbus_ops = {
349*4882a593Smuzhiyun 	.hwbus_memcpy_fromio	= cw1200_spi_memcpy_fromio,
350*4882a593Smuzhiyun 	.hwbus_memcpy_toio	= cw1200_spi_memcpy_toio,
351*4882a593Smuzhiyun 	.lock			= cw1200_spi_lock,
352*4882a593Smuzhiyun 	.unlock			= cw1200_spi_unlock,
353*4882a593Smuzhiyun 	.align_size		= cw1200_spi_align_size,
354*4882a593Smuzhiyun 	.power_mgmt		= cw1200_spi_pm,
355*4882a593Smuzhiyun };
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun /* Probe Function to be called by SPI stack when device is discovered */
cw1200_spi_probe(struct spi_device * func)358*4882a593Smuzhiyun static int cw1200_spi_probe(struct spi_device *func)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun 	const struct cw1200_platform_data_spi *plat_data =
361*4882a593Smuzhiyun 		dev_get_platdata(&func->dev);
362*4882a593Smuzhiyun 	struct hwbus_priv *self;
363*4882a593Smuzhiyun 	int status;
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	/* Sanity check speed */
366*4882a593Smuzhiyun 	if (func->max_speed_hz > 52000000)
367*4882a593Smuzhiyun 		func->max_speed_hz = 52000000;
368*4882a593Smuzhiyun 	if (func->max_speed_hz < 1000000)
369*4882a593Smuzhiyun 		func->max_speed_hz = 1000000;
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	/* Fix up transfer size */
372*4882a593Smuzhiyun 	if (plat_data->spi_bits_per_word)
373*4882a593Smuzhiyun 		func->bits_per_word = plat_data->spi_bits_per_word;
374*4882a593Smuzhiyun 	if (!func->bits_per_word)
375*4882a593Smuzhiyun 		func->bits_per_word = 16;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	/* And finally.. */
378*4882a593Smuzhiyun 	func->mode = SPI_MODE_0;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	pr_info("cw1200_wlan_spi: Probe called (CS %d M %d BPW %d CLK %d)\n",
381*4882a593Smuzhiyun 		func->chip_select, func->mode, func->bits_per_word,
382*4882a593Smuzhiyun 		func->max_speed_hz);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	if (cw1200_spi_on(plat_data)) {
385*4882a593Smuzhiyun 		pr_err("spi_on() failed!\n");
386*4882a593Smuzhiyun 		return -1;
387*4882a593Smuzhiyun 	}
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	if (spi_setup(func)) {
390*4882a593Smuzhiyun 		pr_err("spi_setup() failed!\n");
391*4882a593Smuzhiyun 		return -1;
392*4882a593Smuzhiyun 	}
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	self = devm_kzalloc(&func->dev, sizeof(*self), GFP_KERNEL);
395*4882a593Smuzhiyun 	if (!self) {
396*4882a593Smuzhiyun 		pr_err("Can't allocate SPI hwbus_priv.");
397*4882a593Smuzhiyun 		return -ENOMEM;
398*4882a593Smuzhiyun 	}
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	self->pdata = plat_data;
401*4882a593Smuzhiyun 	self->func = func;
402*4882a593Smuzhiyun 	spin_lock_init(&self->lock);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	spi_set_drvdata(func, self);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	init_waitqueue_head(&self->wq);
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	status = cw1200_spi_irq_subscribe(self);
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	status = cw1200_core_probe(&cw1200_spi_hwbus_ops,
411*4882a593Smuzhiyun 				   self, &func->dev, &self->core,
412*4882a593Smuzhiyun 				   self->pdata->ref_clk,
413*4882a593Smuzhiyun 				   self->pdata->macaddr,
414*4882a593Smuzhiyun 				   self->pdata->sdd_file,
415*4882a593Smuzhiyun 				   self->pdata->have_5ghz);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	if (status) {
418*4882a593Smuzhiyun 		cw1200_spi_irq_unsubscribe(self);
419*4882a593Smuzhiyun 		cw1200_spi_off(plat_data);
420*4882a593Smuzhiyun 	}
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	return status;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun /* Disconnect Function to be called by SPI stack when device is disconnected */
cw1200_spi_disconnect(struct spi_device * func)426*4882a593Smuzhiyun static int cw1200_spi_disconnect(struct spi_device *func)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun 	struct hwbus_priv *self = spi_get_drvdata(func);
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	if (self) {
431*4882a593Smuzhiyun 		cw1200_spi_irq_unsubscribe(self);
432*4882a593Smuzhiyun 		if (self->core) {
433*4882a593Smuzhiyun 			cw1200_core_release(self->core);
434*4882a593Smuzhiyun 			self->core = NULL;
435*4882a593Smuzhiyun 		}
436*4882a593Smuzhiyun 	}
437*4882a593Smuzhiyun 	cw1200_spi_off(dev_get_platdata(&func->dev));
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	return 0;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun 
cw1200_spi_suspend(struct device * dev)442*4882a593Smuzhiyun static int __maybe_unused cw1200_spi_suspend(struct device *dev)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun 	struct hwbus_priv *self = spi_get_drvdata(to_spi_device(dev));
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	if (!cw1200_can_suspend(self->core))
447*4882a593Smuzhiyun 		return -EAGAIN;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	/* XXX notify host that we have to keep CW1200 powered on? */
450*4882a593Smuzhiyun 	return 0;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(cw1200_pm_ops, cw1200_spi_suspend, NULL);
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static struct spi_driver spi_driver = {
456*4882a593Smuzhiyun 	.probe		= cw1200_spi_probe,
457*4882a593Smuzhiyun 	.remove		= cw1200_spi_disconnect,
458*4882a593Smuzhiyun 	.driver = {
459*4882a593Smuzhiyun 		.name		= "cw1200_wlan_spi",
460*4882a593Smuzhiyun 		.pm		= IS_ENABLED(CONFIG_PM) ? &cw1200_pm_ops : NULL,
461*4882a593Smuzhiyun 	},
462*4882a593Smuzhiyun };
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun module_spi_driver(spi_driver);
465