| /OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/jpege/ |
| H A D | hal_jpege_vepu540c.c | 236 MppDevRegRdCfg cfg1; in hal_jpege_v540c_start() local
275 cfg1.reg = ®_out->hw_status; in hal_jpege_v540c_start()
276 cfg1.size = sizeof(RK_U32); in hal_jpege_v540c_start()
277 cfg1.offset = VEPU540C_REG_BASE_HW_STATUS; in hal_jpege_v540c_start()
279 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_jpege_v540c_start()
285 cfg1.reg = ®_out->st; in hal_jpege_v540c_start()
286 cfg1.size = sizeof(JpegV540cStatus) - 4; in hal_jpege_v540c_start()
287 cfg1.offset = VEPU540C_STATUS_OFFSET; in hal_jpege_v540c_start()
289 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_jpege_v540c_start()
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| /OK3568_Linux_fs/kernel/drivers/tty/serial/ |
| H A D | msm_geni_serial_earlycon.c | 136 bool msb_to_lsb, unsigned long *cfg0, unsigned long *cfg1) in se_get_packing_config_earlycon() argument
150 *cfg1 = 0; in se_get_packing_config_earlycon()
166 *cfg1 = cfg[2] | (cfg[3] << 10); in se_get_packing_config_earlycon()
306 unsigned long cfg0, cfg1; in msm_geni_serial_earlycon_setup() local
335 se_get_packing_config_earlycon(8, 1, false, &cfg0, &cfg1); in msm_geni_serial_earlycon_setup()
341 writel_relaxed(cfg1, uport->membase + SE_GENI_TX_PACKING_CFG1); in msm_geni_serial_earlycon_setup()
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| /OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/ |
| H A D | ni_at_ao.c | 108 unsigned short cfg1; member
120 devpriv->cfg1 |= ATAO_CFG1_GRP2WR; in atao_select_reg_group()
122 devpriv->cfg1 &= ~ATAO_CFG1_GRP2WR; in atao_select_reg_group()
123 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_select_reg_group()
271 devpriv->cfg1 = 0; in atao_reset()
272 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_reset()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/exynos/ |
| H A D | exynos_drm_fimc.c | 421 u32 cfg1, cfg2; in fimc_src_set_transf() local
425 cfg1 = fimc_read(ctx, EXYNOS_MSCTRL); in fimc_src_set_transf()
426 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | in fimc_src_set_transf()
435 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf()
437 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf()
442 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf()
444 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf()
447 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | in fimc_src_set_transf()
450 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf()
452 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | arb.c | 202 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); in nv04_update_arb() local
224 sim_data.mem_latency = cfg1 & 0xf; in nv04_update_arb()
225 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); in nv04_update_arb()
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/mach-imx/ |
| H A D | boot_mode.h | 9 #define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \ argument
10 ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
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| /OK3568_Linux_fs/u-boot/drivers/net/ |
| H A D | pic32_eth.c | 76 writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */ in pic32_mii_init()
78 writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */ in pic32_mii_init()
173 writel(v, &emac_p->cfg1.raw); in pic32_mac_init()
220 writel(EMAC_SOFTRESET, &emac_p->cfg1.raw); in pic32_mac_reset()
224 writel(0, &emac_p->cfg1.raw); in pic32_mac_reset()
367 writel(EMAC_SOFTRESET, &emac_p->cfg1.raw); in pic32_eth_stop()
370 writel(0, &emac_p->cfg1.raw); in pic32_eth_stop()
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| /OK3568_Linux_fs/kernel/drivers/media/platform/atmel/ |
| H A D | atmel-isi.c | 361 u32 ctrl, cfg1; in start_dma() local
363 cfg1 = isi_readl(isi, ISI_CFG1); in start_dma()
388 cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK; in start_dma()
390 cfg1 |= isi->pdata.frate | ISI_CFG1_DISCR; in start_dma()
399 isi_writel(isi, ISI_CFG1, cfg1); in start_dma()
788 u32 cfg1 = 0; in isi_camera_set_bus_param() local
792 cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW; in isi_camera_set_bus_param()
794 cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW; in isi_camera_set_bus_param()
796 cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING; in isi_camera_set_bus_param()
798 cfg1 |= ISI_CFG1_EMB_SYNC; in isi_camera_set_bus_param()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/zte/ |
| H A D | clk-zx296702.c | 53 { .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
54 { .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa },
55 { .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 },
56 { .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 },
57 { .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa },
58 { .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 },
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| H A D | clk.h | 17 u32 cfg1; member
34 .cfg1 = _cfg1, \
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x2/ |
| H A D | phy.c | 187 u32 cfg0, cfg1; in mt76x2_configure_tx_delay() local
191 cfg1 = 0x00011414; in mt76x2_configure_tx_delay()
194 cfg1 = 0x00021414; in mt76x2_configure_tx_delay()
197 mt76_wr(dev, MT_TX_SW_CFG1, cfg1); in mt76x2_configure_tx_delay()
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| /OK3568_Linux_fs/kernel/drivers/iio/adc/ |
| H A D | imx7d_adc.c | 233 u32 cfg1 = 0; in imx7d_adc_channel_set() local
240 cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN | in imx7d_adc_channel_set()
250 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel); in imx7d_adc_channel_set()
267 writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel); in imx7d_adc_channel_set()
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| /OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h265e/ |
| H A D | hal_h265e_vepu541.c | 1747 MppDevRegRdCfg cfg1; in hal_h265e_v540_start() local
1787 cfg1.reg = ®_out->hw_status; in hal_h265e_v540_start()
1788 cfg1.size = sizeof(RK_U32); in hal_h265e_v540_start()
1789 cfg1.offset = VEPU541_REG_BASE_HW_STATUS; in hal_h265e_v540_start()
1791 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v540_start()
1797 cfg1.reg = ®_out->st_bsl; in hal_h265e_v540_start()
1798 cfg1.size = sizeof(H265eV541IoctlOutputElem) - 4; in hal_h265e_v540_start()
1799 cfg1.offset = VEPU541_REG_BASE_STATISTICS; in hal_h265e_v540_start()
1801 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v540_start()
1877 MppDevRegRdCfg cfg1; in hal_h265e_v541_start() local
[all …]
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| /OK3568_Linux_fs/kernel/drivers/soc/qcom/ |
| H A D | qcom-geni-se.c | 398 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; in geni_se_config_packing() local
427 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); in geni_se_config_packing()
431 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); in geni_se_config_packing()
435 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); in geni_se_config_packing()
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| /OK3568_Linux_fs/kernel/drivers/video/fbdev/nvidia/ |
| H A D | nv_hw.c | 387 unsigned int MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings()
397 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv4UpdateArbitrationSettings()
400 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); in nv4UpdateArbitrationSettings()
626 unsigned int MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings()
637 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv10UpdateArbitrationSettings()
640 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); in nv10UpdateArbitrationSettings()
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/agere/ |
| H A D | et131x.c | 819 ¯egs->cfg1); in et1310_config_mac_regs1()
861 writel(0, ¯egs->cfg1); in et1310_config_mac_regs1()
869 u32 cfg1; in et1310_config_mac_regs2() local
875 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
889 cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE | in et1310_config_mac_regs2()
892 cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW); in et1310_config_mac_regs2()
894 cfg1 |= ET_MAC_CFG1_RX_FLOW; in et1310_config_mac_regs2()
895 writel(cfg1, &mac->cfg1); in et1310_config_mac_regs2()
921 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
922 } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100); in et1310_config_mac_regs2()
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/m5208evbe/ |
| H A D | m5208evbe.c | 42 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /OK3568_Linux_fs/u-boot/board/freescale/m53017evb/ |
| H A D | m53017evb.c | 42 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /OK3568_Linux_fs/u-boot/board/freescale/m5373evb/ |
| H A D | m5373evb.c | 39 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /OK3568_Linux_fs/u-boot/board/freescale/m5329evb/ |
| H A D | m5329evb.c | 39 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /OK3568_Linux_fs/kernel/sound/pci/ |
| H A D | als4000.c | 692 u32 cfg1 = 0; in snd_als4000_set_addr() local
700 cfg1 |= (game_io | 1) << 16; in snd_als4000_set_addr()
702 cfg1 |= (opl_io | 1); in snd_als4000_set_addr()
703 snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA8_LEGACY_CFG1, cfg1); in snd_als4000_set_addr()
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| /OK3568_Linux_fs/kernel/arch/sparc/include/asm/ |
| H A D | sbi.h | 21 /* 0x0014 */ u32 cfg1; /* Slot1 config reg */ member
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| /OK3568_Linux_fs/u-boot/board/freescale/m548xevb/ |
| H A D | m548xevb.c | 56 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /OK3568_Linux_fs/u-boot/board/freescale/m547xevb/ |
| H A D | m547xevb.c | 56 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ |
| H A D | qcom_nandc.c | 300 __le32 cfg1; member
448 u32 cfg0, cfg1; member
620 return ®s->cfg1; in offset_to_nandc_reg()
684 u32 cmd, cfg0, cfg1, ecc_bch_cfg; in update_rw_regs() local
699 cfg1 = host->cfg1; in update_rw_regs()
705 cfg1 = host->cfg1_raw; in update_rw_regs()
711 nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1); in update_rw_regs()
2584 host->cfg1 = 7 << NAND_RECOVERY_CYCLES in qcom_nand_attach_chip()
2623 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, in qcom_nand_attach_chip()
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