1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5 #include <linux/console.h>
6 #include <linux/delay.h>
7 #include <linux/io.h>
8 #include <linux/serial_core.h>
9
10 #define SE_GENI_DMA_MODE_EN 0x258
11 #define SE_UART_TX_TRANS_CFG 0x25C
12 #define SE_UART_TX_WORD_LEN 0x268
13 #define SE_UART_TX_STOP_BIT_LEN 0x26C
14 #define SE_UART_TX_TRANS_LEN 0x270
15 #define SE_UART_TX_PARITY_CFG 0x2A4
16 /* SE_UART_TRANS_CFG */
17 #define UART_CTS_MASK BIT(1)
18 /* UART M_CMD OP codes */
19 #define UART_START_TX 0x1
20
21 #define UART_OVERSAMPLING 32
22 #define DEF_FIFO_DEPTH_WORDS 16
23 #define DEF_TX_WM 2
24 #define DEF_FIFO_WIDTH_BITS 32
25
26 #define GENI_FORCE_DEFAULT_REG 0x20
27 #define GENI_OUTPUT_CTRL 0x24
28 #define GENI_CGC_CTRL 0x28
29 #define GENI_SER_M_CLK_CFG 0x48
30 #define GENI_FW_REVISION_RO 0x68
31
32 #define SE_GENI_TX_PACKING_CFG0 0x260
33 #define SE_GENI_TX_PACKING_CFG1 0x264
34 #define SE_GENI_M_CMD0 0x600
35 #define SE_GENI_M_CMD_CTRL_REG 0x604
36 #define SE_GENI_M_IRQ_STATUS 0x610
37 #define SE_GENI_M_IRQ_EN 0x614
38 #define SE_GENI_M_IRQ_CLEAR 0x618
39 #define SE_GENI_TX_FIFOn 0x700
40 #define SE_GENI_TX_WATERMARK_REG 0x80C
41
42 #define SE_IRQ_EN 0xE1C
43 #define SE_HW_PARAM_0 0xE24
44 #define SE_HW_PARAM_1 0xE28
45
46 /* GENI_OUTPUT_CTRL fields */
47 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
48
49 /* GENI_FORCE_DEFAULT_REG fields */
50 #define FORCE_DEFAULT BIT(0)
51
52 /* GENI_CGC_CTRL fields */
53 #define CFG_AHB_CLK_CGC_ON BIT(0)
54 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
55 #define DATA_AHB_CLK_CGC_ON BIT(2)
56 #define SCLK_CGC_ON BIT(3)
57 #define TX_CLK_CGC_ON BIT(4)
58 #define RX_CLK_CGC_ON BIT(5)
59 #define EXT_CLK_CGC_ON BIT(6)
60 #define PROG_RAM_HCLK_OFF BIT(8)
61 #define PROG_RAM_SCLK_OFF BIT(9)
62 #define DEFAULT_CGC_EN GENMASK(6, 0)
63
64 /* GENI_STATUS fields */
65 #define M_GENI_CMD_ACTIVE BIT(0)
66
67 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
68 #define SER_CLK_EN BIT(0)
69 #define CLK_DIV_MSK GENMASK(15, 4)
70 #define CLK_DIV_SHFT 4
71
72 /* CLK_CTRL_RO fields */
73
74 /* FIFO_IF_DISABLE_RO fields */
75 #define FIFO_IF_DISABLE BIT(0)
76
77 /* FW_REVISION_RO fields */
78 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
79 #define FW_REV_PROTOCOL_SHFT 8
80 #define FW_REV_VERSION_MSK GENMASK(7, 0)
81
82 /* GENI_CLK_SEL fields */
83 #define CLK_SEL_MSK GENMASK(2, 0)
84
85 /* SE_GENI_DMA_MODE_EN */
86 #define GENI_DMA_MODE_EN BIT(0)
87
88 /* GENI_M_CMD0 fields */
89 #define M_OPCODE_MSK GENMASK(31, 27)
90 #define M_OPCODE_SHFT 27
91 #define M_PARAMS_MSK GENMASK(26, 0)
92
93 /* GENI_M_CMD_CTRL_REG */
94 #define M_GENI_CMD_CANCEL BIT(2)
95 #define M_GENI_CMD_ABORT BIT(1)
96 #define M_GENI_DISABLE BIT(0)
97
98 /* GENI_M_IRQ_EN fields */
99 #define M_CMD_DONE_EN BIT(0)
100 #define M_CMD_OVERRUN_EN BIT(1)
101 #define M_ILLEGAL_CMD_EN BIT(2)
102 #define M_CMD_FAILURE_EN BIT(3)
103 #define M_CMD_CANCEL_EN BIT(4)
104 #define M_CMD_ABORT_EN BIT(5)
105 #define M_TIMESTAMP_EN BIT(6)
106 #define M_GP_SYNC_IRQ_0_EN BIT(8)
107 #define M_IO_DATA_DEASSERT_EN BIT(22)
108 #define M_IO_DATA_ASSERT_EN BIT(23)
109 #define M_TX_FIFO_RD_ERR_EN BIT(28)
110 #define M_TX_FIFO_WR_ERR_EN BIT(29)
111 #define M_TX_FIFO_WATERMARK_EN BIT(30)
112 #define M_SEC_IRQ_EN BIT(31)
113 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
114 M_IO_DATA_DEASSERT_EN | \
115 M_IO_DATA_ASSERT_EN | M_TX_FIFO_RD_ERR_EN | \
116 M_TX_FIFO_WR_ERR_EN)
117
118 /* GENI_TX_FIFO_STATUS fields */
119 #define TX_FIFO_WC GENMASK(27, 0)
120
121 /* SE_IRQ_EN fields */
122 #define GENI_M_IRQ_EN BIT(2)
123
124 #define UART_PROTOCOL 2
125
get_se_proto_earlycon(void __iomem * base)126 static int get_se_proto_earlycon(void __iomem *base)
127 {
128 int proto;
129
130 proto = ((readl_relaxed(base + GENI_FW_REVISION_RO)
131 & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT);
132 return proto;
133 }
134
se_get_packing_config_earlycon(int bpw,int pack_words,bool msb_to_lsb,unsigned long * cfg0,unsigned long * cfg1)135 static void se_get_packing_config_earlycon(int bpw, int pack_words,
136 bool msb_to_lsb, unsigned long *cfg0, unsigned long *cfg1)
137 {
138 u32 cfg[4] = {0};
139 int len, i;
140 int temp_bpw = bpw;
141 int idx_start = (msb_to_lsb ? (bpw - 1) : 0);
142 int idx_delta = (msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE);
143 int ceil_bpw = ((bpw & (BITS_PER_BYTE - 1)) ?
144 ((bpw & ~(BITS_PER_BYTE - 1)) + BITS_PER_BYTE) : bpw);
145 int iter = (ceil_bpw * pack_words) >> 3;
146 int idx = idx_start;
147
148 if (iter <= 0 || iter > 4) {
149 *cfg0 = 0;
150 *cfg1 = 0;
151 return;
152 }
153
154 for (i = 0; i < iter; i++) {
155 len = (temp_bpw < BITS_PER_BYTE) ?
156 (temp_bpw - 1) : BITS_PER_BYTE - 1;
157 cfg[i] = ((idx << 5) | (msb_to_lsb << 4) | (len << 1));
158 idx = ((temp_bpw - BITS_PER_BYTE) <= 0) ?
159 ((i + 1) * BITS_PER_BYTE) + idx_start :
160 idx + idx_delta;
161 temp_bpw = ((temp_bpw - BITS_PER_BYTE) <= 0) ?
162 bpw : (temp_bpw - BITS_PER_BYTE);
163 }
164 cfg[iter - 1] |= 1;
165 *cfg0 = cfg[0] | (cfg[1] << 10);
166 *cfg1 = cfg[2] | (cfg[3] << 10);
167 }
168
se_io_init_earlycon(void __iomem * base)169 static void se_io_init_earlycon(void __iomem *base)
170 {
171 u32 io_op_ctrl;
172 u32 geni_cgc_ctrl;
173
174 geni_cgc_ctrl = readl_relaxed(base + GENI_CGC_CTRL);
175 geni_cgc_ctrl |= DEFAULT_CGC_EN;
176 io_op_ctrl = DEFAULT_IO_OUTPUT_CTRL_MSK;
177 writel_relaxed(geni_cgc_ctrl, base + GENI_CGC_CTRL);
178
179 writel_relaxed(io_op_ctrl, base + GENI_OUTPUT_CTRL);
180 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
181 }
182
geni_se_select_fifo_mode_earlycon(void __iomem * base)183 static void geni_se_select_fifo_mode_earlycon(void __iomem *base)
184 {
185 u32 val;
186
187 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
188 val &= ~GENI_DMA_MODE_EN;
189 writel_relaxed(val, base + SE_GENI_M_IRQ_EN);
190 }
191
msm_geni_serial_wr_char(struct uart_port * uport,int ch)192 static void msm_geni_serial_wr_char(struct uart_port *uport, int ch)
193 {
194 writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
195 }
196
msm_geni_serial_poll_bit(struct uart_port * uport,int offset,int bit_field,bool set)197 static int msm_geni_serial_poll_bit(struct uart_port *uport,
198 int offset, int bit_field, bool set)
199 {
200 int iter = 0;
201 bool met = false, cond = false;
202 unsigned int reg, total_iter = 1000;
203
204 while (iter < total_iter) {
205 reg = readl_relaxed(uport->membase + offset);
206 cond = reg & bit_field;
207 if (cond == set) {
208 met = true;
209 break;
210 }
211 udelay(10);
212 iter++;
213 }
214 return met;
215 }
216
msm_geni_serial_poll_abort_tx(struct uart_port * uport)217 static void msm_geni_serial_poll_abort_tx(struct uart_port *uport)
218 {
219 int done = 0;
220 u32 irq_clear = M_CMD_DONE_EN;
221
222 done = msm_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
223 M_CMD_DONE_EN, true);
224 if (!done) {
225 writel_relaxed(M_GENI_CMD_ABORT,
226 uport->membase + SE_GENI_M_CMD_CTRL_REG);
227 irq_clear |= M_CMD_ABORT_EN;
228 msm_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
229 M_CMD_ABORT_EN, true);
230 }
231 writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
232 }
233
msm_geni_serial_setup_tx(struct uart_port * uport,unsigned int xmit_size)234 static void msm_geni_serial_setup_tx(struct uart_port *uport,
235 unsigned int xmit_size)
236 {
237 u32 m_cmd = 0;
238
239 writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
240 m_cmd |= (UART_START_TX << M_OPCODE_SHFT);
241 writel_relaxed(m_cmd, uport->membase + SE_GENI_M_CMD0);
242 }
243
244 static void
__msm_geni_serial_console_write(struct uart_port * uport,const char * s,unsigned int count)245 __msm_geni_serial_console_write(struct uart_port *uport, const char *s,
246 unsigned int count)
247 {
248 int new_line = 0;
249 int i;
250 int bytes_to_send = count;
251 int fifo_depth = DEF_FIFO_DEPTH_WORDS;
252 int tx_wm = DEF_TX_WM;
253
254 for (i = 0; i < count; i++) {
255 if (s[i] == '\n')
256 new_line++;
257 }
258
259 bytes_to_send += new_line;
260 writel_relaxed(tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
261 msm_geni_serial_setup_tx(uport, bytes_to_send);
262 i = 0;
263 while (i < count) {
264 u32 chars_to_write = 0;
265 u32 avail_fifo_bytes = (fifo_depth - tx_wm);
266 /*
267 * If the WM bit never set, then the Tx state machine is not
268 * in a valid state, so break, cancel/abort any existing
269 * command. Unfortunately the current data being written is
270 * lost.
271 */
272 while (!msm_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
273 M_TX_FIFO_WATERMARK_EN, true))
274 break;
275 chars_to_write = min((unsigned int)(count - i),
276 avail_fifo_bytes);
277 if ((chars_to_write << 1) > avail_fifo_bytes)
278 chars_to_write = (avail_fifo_bytes >> 1);
279 uart_console_write(uport, (s + i), chars_to_write,
280 msm_geni_serial_wr_char);
281 writel_relaxed(M_TX_FIFO_WATERMARK_EN,
282 uport->membase + SE_GENI_M_IRQ_CLEAR);
283 i += chars_to_write;
284 }
285 msm_geni_serial_poll_abort_tx(uport);
286 }
287
288 static void
msm_geni_serial_early_console_write(struct console * con,const char * s,unsigned int n)289 msm_geni_serial_early_console_write(struct console *con, const char *s,
290 unsigned int n)
291 {
292 struct earlycon_device *dev = con->data;
293
294 __msm_geni_serial_console_write(&dev->port, s, n);
295 }
296
297 static int __init
msm_geni_serial_earlycon_setup(struct earlycon_device * dev,const char * opt)298 msm_geni_serial_earlycon_setup(struct earlycon_device *dev,
299 const char *opt)
300 {
301 int ret = 0;
302 u32 tx_trans_cfg = 0;
303 u32 tx_parity_cfg = 0;
304 u32 stop_bit = 0;
305 u32 bits_per_char = 0;
306 unsigned long cfg0, cfg1;
307 struct uart_port *uport = &dev->port;
308
309 if (!uport->membase) {
310 ret = -ENOMEM;
311 goto exit;
312 }
313
314 if (get_se_proto_earlycon(uport->membase) != UART_PROTOCOL) {
315 ret = -ENXIO;
316 goto exit;
317 }
318
319 /*
320 * Ignore Flow control.
321 * Disable Tx Parity.
322 * Don't check Parity during Rx.
323 * Disable Rx Parity.
324 * n = 8.
325 * Stop bit = 0.
326 * Stale timeout in bit-time (3 chars worth).
327 */
328 tx_trans_cfg |= UART_CTS_MASK;
329 tx_parity_cfg = 0;
330 bits_per_char = 0x8;
331 stop_bit = 0;
332
333 msm_geni_serial_poll_abort_tx(uport);
334
335 se_get_packing_config_earlycon(8, 1, false, &cfg0, &cfg1);
336
337 se_io_init_earlycon(uport->membase);
338
339 geni_se_select_fifo_mode_earlycon(uport->membase);
340 writel_relaxed(cfg0, uport->membase + SE_GENI_TX_PACKING_CFG0);
341 writel_relaxed(cfg1, uport->membase + SE_GENI_TX_PACKING_CFG1);
342 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
343 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
344 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
345 writel_relaxed(stop_bit, uport->membase + SE_UART_TX_STOP_BIT_LEN);
346
347 dev->con->write = msm_geni_serial_early_console_write;
348 dev->con->setup = NULL;
349 exit:
350 return ret;
351 }
352
353 OF_EARLYCON_DECLARE(msm_geni_serial, "qcom,msm-geni-console",
354 msm_geni_serial_earlycon_setup);
355