1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <config.h>
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/immap.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
checkboard(void)18*4882a593Smuzhiyun int checkboard(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun puts("Board: ");
21*4882a593Smuzhiyun puts("Freescale M53017EVB\n");
22*4882a593Smuzhiyun return 0;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
dram_init(void)25*4882a593Smuzhiyun int dram_init(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
28*4882a593Smuzhiyun u32 dramsize, i;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun for (i = 0x13; i < 0x20; i++) {
33*4882a593Smuzhiyun if (dramsize == (1 << i))
34*4882a593Smuzhiyun break;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun i--;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
39*4882a593Smuzhiyun #ifdef CONFIG_SYS_SDRAM_BASE1
40*4882a593Smuzhiyun out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
41*4882a593Smuzhiyun #endif
42*4882a593Smuzhiyun out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
43*4882a593Smuzhiyun out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun udelay(500);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Issue PALL */
48*4882a593Smuzhiyun out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
49*4882a593Smuzhiyun asm("nop");
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Perform two refresh cycles */
52*4882a593Smuzhiyun out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
53*4882a593Smuzhiyun out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
54*4882a593Smuzhiyun asm("nop");
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Issue LEMR */
57*4882a593Smuzhiyun out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
58*4882a593Smuzhiyun asm("nop");
59*4882a593Smuzhiyun out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
60*4882a593Smuzhiyun asm("nop");
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
63*4882a593Smuzhiyun asm("nop");
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun out_be32(&sdram->ctrl,
66*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
67*4882a593Smuzhiyun asm("nop");
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun udelay(100);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun gd->ram_size = dramsize;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
testdram(void)76*4882a593Smuzhiyun int testdram(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun /* TODO: XXX XXX XXX */
79*4882a593Smuzhiyun printf("DRAM test not implemented!\n");
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return (0);
82*4882a593Smuzhiyun }
83