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Searched refs:bit8 (Results 1 – 22 of 22) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/staging/media/atomisp/pci/hive_isp_css_include/
H A Dmath_support.h51 #define bit8(x) (bit4(x) | (bit4(x) >> 4)) macro
52 #define bit16(x) (bit8(x) | (bit8(x) >> 8))
/OK3568_Linux_fs/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg58 # bit8-7: TR2R
92 # bit8: 0, DLL reset=0 normal
115 # bit8 : 0
/OK3568_Linux_fs/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg56 # bit8-7: TR2R
89 # bit8: 0, DLL reset=0 normal
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg59 # bit8-7: TR2R
92 # bit8: 0, DLL reset=0 normal
114 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg60 # bit8-7: TR2R
93 # bit8: 0, DLL reset=0 normal
115 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg57 # bit8-7: TR2R
90 # bit8: 0, DLL reset=0 normal
112 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg62 # bit8-7: TR2R
95 # bit8: 0, DLL reset=0 normal
117 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg56 # bit8-7: TR2R
89 # bit8: 0, DLL reset=0 normal
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg56 # bit8-7: TR2R
89 # bit8: 0x0, DLL reset=0 normal
111 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg56 # bit8-7: TR2R
89 # bit8: 0, DLL reset=0 normal
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg56 # bit8-7: TR2R
89 # bit8: 0, DLL reset=0 normal
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg57 # bit8-7: TR2R
90 # bit8: 0x0, DLL reset=0 normal
112 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage-ns2l.cfg56 # bit8-7: TR2R
89 # bit8: 0, DLL reset=0 normal
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
H A Dkwbimage-is2.cfg56 # bit8-7: TR2R
89 # bit8: 0, DLL reset=0 normal
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
H A Dkwbimage.cfg56 # bit8-7: TR2R
89 # bit8: 0, DLL reset=0 normal
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg60 # bit8-7: TR2R
93 # bit8: 0, DLL reset=0 normal
115 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg70 # bit8-7: 0, 1 cycle tR2R
107 # bit8: 0, (Reset DLL) Normal operation
131 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
H A Dkwbimage-lsxhl.cfg70 # bit8-7: 0, 1 cycle tR2R
107 # bit8: 0, (Reset DLL) Normal operation
131 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/kernel/drivers/input/touchscreen/focaltech_touch/
H A Dfocaltech_upgrade_ft8201.c72 u16 bit8: 1; member
151 …ecc.bits.bit0 = ecc_last.bits.bit8 ^ ecc_last.bits.bit9 ^ ecc_last.bits.bit10 ^ ecc_last.bits.bit11 in cal_lcdinitcode_ecc()
161 …ecc.bits.bit2 = ecc_last.bits.bit8 ^ ecc_last.bits.bit9 ^ temp_byte.bits.bit0 ^ temp_byte.bits.bit… in cal_lcdinitcode_ecc()
173 …ecc.bits.bit8 = ecc_last.bits.bit0 ^ ecc_last.bits.bit14 ^ ecc_last.bits.bit15 ^ temp_byte.bits.bi… in cal_lcdinitcode_ecc()
187 …ecc.bits.bit15 = ecc_last.bits.bit7 ^ ecc_last.bits.bit8 ^ ecc_last.bits.bit9 ^ ecc_last.bits.bit10 in cal_lcdinitcode_ecc()
/OK3568_Linux_fs/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg66 # bit8-7: 0, 1 cycle tR2R
99 # bit8: 0, (Reset DLL) Normal operation
121 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg77 # bit8-7: TR2R
123 # bit8 : 0 , no sample stage
H A Dkwbimage-memphis.cfg80 # bit8-7: TR2R
126 # bit8 : 1 , add a sample stage