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Searched refs:SUNXI_DRAM_CTL0_BASE (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a83t.h147 #define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
148 #define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
149 #define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)
151 #define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
152 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
153 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
154 #define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
155 #define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
157 #define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x))
158 #define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x)
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H A Ddram_sun8i_a33.h146 #define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
147 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
148 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
149 #define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
150 #define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
H A Dcpu_sun9i.h46 #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) macro
H A Dcpu_sun4i.h156 #define SUNXI_DRAM_CTL0_BASE 0x01c63000 macro
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a33.c90 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in auto_set_timing_para()
174 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_pir()
183 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_data_train_cfg()
194 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_train_dram()
205 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
300 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()
333 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
H A Ddram_sun8i_a83t.c89 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in auto_set_timing_para()
206 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_pir()
215 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_data_train_cfg()
226 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_train_dram()
261 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
394 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()
431 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
H A Ddram_sunxi_dw.c22 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_phy_init()
31 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_bit_delays()
271 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_h3_zq_calibration_quirk()
370 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()
425 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
690 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
H A Ddram_sun9i.c288 mctl_ctl_sched_init(SUNXI_DRAM_CTL0_BASE); in mctl_sys_init()
455 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
H A Ddram_sun8i_a23.c98 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_init()
H A Ddram_sun6i.c111 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr3_1333.c8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()
H A Dlpddr3_stock.c8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()
H A Dddr2_v3s.c8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()