1*4882a593Smuzhiyun #include <common.h>
2*4882a593Smuzhiyun #include <asm/arch/dram.h>
3*4882a593Smuzhiyun #include <asm/arch/cpu.h>
4*4882a593Smuzhiyun
mctl_set_timing_params(uint16_t socid,struct dram_para * para)5*4882a593Smuzhiyun void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
6*4882a593Smuzhiyun {
7*4882a593Smuzhiyun struct sunxi_mctl_ctl_reg * const mctl_ctl =
8*4882a593Smuzhiyun (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun u8 tccd = 2;
11*4882a593Smuzhiyun u8 tfaw = ns_to_t(50);
12*4882a593Smuzhiyun u8 trrd = max(ns_to_t(10), 4);
13*4882a593Smuzhiyun u8 trcd = ns_to_t(15);
14*4882a593Smuzhiyun u8 trc = ns_to_t(53);
15*4882a593Smuzhiyun u8 txp = max(ns_to_t(8), 3);
16*4882a593Smuzhiyun u8 twtr = max(ns_to_t(8), 4);
17*4882a593Smuzhiyun u8 trtp = max(ns_to_t(8), 4);
18*4882a593Smuzhiyun u8 twr = max(ns_to_t(15), 3);
19*4882a593Smuzhiyun u8 trp = ns_to_t(15);
20*4882a593Smuzhiyun u8 tras = ns_to_t(38);
21*4882a593Smuzhiyun u16 trefi = ns_to_t(7800) / 32;
22*4882a593Smuzhiyun u16 trfc = ns_to_t(350);
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun u8 tmrw = 0;
25*4882a593Smuzhiyun u8 tmrd = 4;
26*4882a593Smuzhiyun u8 tmod = 12;
27*4882a593Smuzhiyun u8 tcke = 3;
28*4882a593Smuzhiyun u8 tcksrx = 5;
29*4882a593Smuzhiyun u8 tcksre = 5;
30*4882a593Smuzhiyun u8 tckesr = 4;
31*4882a593Smuzhiyun u8 trasmax = 24;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun u8 tcl = 6; /* CL 12 */
34*4882a593Smuzhiyun u8 tcwl = 4; /* CWL 8 */
35*4882a593Smuzhiyun u8 t_rdata_en = 4;
36*4882a593Smuzhiyun u8 wr_latency = 2;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
39*4882a593Smuzhiyun u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
40*4882a593Smuzhiyun u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
41*4882a593Smuzhiyun u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
44*4882a593Smuzhiyun u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
45*4882a593Smuzhiyun u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* set mode register */
48*4882a593Smuzhiyun writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
49*4882a593Smuzhiyun writel(0x40, &mctl_ctl->mr[1]);
50*4882a593Smuzhiyun writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
51*4882a593Smuzhiyun writel(0x0, &mctl_ctl->mr[3]);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (socid == SOCID_R40)
54*4882a593Smuzhiyun writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* set DRAM timing */
57*4882a593Smuzhiyun writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
58*4882a593Smuzhiyun DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
59*4882a593Smuzhiyun &mctl_ctl->dramtmg[0]);
60*4882a593Smuzhiyun writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
61*4882a593Smuzhiyun &mctl_ctl->dramtmg[1]);
62*4882a593Smuzhiyun writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
63*4882a593Smuzhiyun DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
64*4882a593Smuzhiyun &mctl_ctl->dramtmg[2]);
65*4882a593Smuzhiyun writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
66*4882a593Smuzhiyun &mctl_ctl->dramtmg[3]);
67*4882a593Smuzhiyun writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
68*4882a593Smuzhiyun DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
69*4882a593Smuzhiyun writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
70*4882a593Smuzhiyun DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
71*4882a593Smuzhiyun &mctl_ctl->dramtmg[5]);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* set two rank timing */
74*4882a593Smuzhiyun clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
75*4882a593Smuzhiyun ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* set PHY interface timing, write latency and read latency configure */
78*4882a593Smuzhiyun writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
79*4882a593Smuzhiyun (wr_latency << 0), &mctl_ctl->pitmg[0]);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* set PHY timing, PTR0-2 use default */
82*4882a593Smuzhiyun writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
83*4882a593Smuzhiyun writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* set refresh timing */
86*4882a593Smuzhiyun writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
87*4882a593Smuzhiyun }
88