Searched refs:PLL2 (Results 1 – 12 of 12) sorted by relevance
| /OK3568_Linux_fs/kernel/sound/soc/codecs/ |
| H A D | ak4642.c | 114 #define PLL2 (1 << 6) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
345 pll = PLL2; in ak4642_dai_set_sysclk()
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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| /OK3568_Linux_fs/u-boot/drivers/video/tegra124/ |
| H A D | sor.c | 489 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
510 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
521 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
527 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
565 DUMP_REG(PLL2); in dump_sor_reg()
702 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
716 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
726 if (tegra_dc_sor_poll_register(sor, PLL2, in tegra_dc_sor_enable_dp()
734 tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | in tegra_dc_sor_enable_dp()
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| H A D | sor.h | 256 #define PLL2 0x19 macro
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | ti,cdce925.txt | 30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
49 PLL2 {
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| H A D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 127 #define PLL2 118 macro
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| H A D | stm32mp1-clks.h | 184 #define PLL2 177 macro
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| /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/ |
| H A D | zl10039.c | 41 PLL2, enumerator
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
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| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | Kconfig | 188 Y4 and Y5 derive from PLL2
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| H A D | clk-stm32mp1.c | 1687 PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
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| /OK3568_Linux_fs/kernel/drivers/clk/qcom/ |
| H A D | mmcc-msm8960.c | 2717 [PLL2] = &pll2.clkr,
2893 [PLL2] = &pll2.clkr,
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