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Searched refs:PLL0 (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dak4642.c116 #define PLL0 (1 << 4) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dzl10039.c39 PLL0 = 0, enumerator
218 ret = zl10039_write(state, PLL0, buf, sizeof(buf)); in zl10039_set_params()
/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Dsor.c496 tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */ in tegra_dc_sor_power_up()
516 tegra_sor_write_field(sor, PLL0, in tegra_dc_sor_power_up()
563 DUMP_REG(PLL0); in dump_sor_reg()
710 tegra_sor_writel(sor, PLL0, in tegra_dc_sor_enable_dp()
H A Dsor.h222 #define PLL0 0x17 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dqcom,gcc-msm8660.h256 #define PLL0 247 macro
H A Dqcom,gcc-ipq806x.h229 #define PLL0 220 macro
H A Dqcom,gcc-mdm9615.h286 #define PLL0 276 macro
H A Dqcom,gcc-msm8960.h284 #define PLL0 276 macro
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/st/
H A Dst,flexgen.txt21 | | |PLL0 | | | | |Dividers| |Dividers| | |
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/
H A Dgcw0.dts448 * PLL0 frequency on demand without having to suspend peripherals.
451 * Put the GPU under PLL0 since we want a higher frequency.
/OK3568_Linux_fs/u-boot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg17 ; This section allows setting the PLL0 system clock with a
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dgcc-mdm9615.c1589 [PLL0] = &pll0.clkr,
H A Dgcc-ipq806x.c2756 [PLL0] = &pll0.clkr,