1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_GCC_8960_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define AFAB_CLK_SRC 0 10*4882a593Smuzhiyun #define AFAB_CORE_CLK 1 11*4882a593Smuzhiyun #define SFAB_MSS_Q6_SW_A_CLK 2 12*4882a593Smuzhiyun #define SFAB_MSS_Q6_FW_A_CLK 3 13*4882a593Smuzhiyun #define QDSS_STM_CLK 4 14*4882a593Smuzhiyun #define SCSS_A_CLK 5 15*4882a593Smuzhiyun #define SCSS_H_CLK 6 16*4882a593Smuzhiyun #define SCSS_XO_SRC_CLK 7 17*4882a593Smuzhiyun #define AFAB_EBI1_CH0_A_CLK 8 18*4882a593Smuzhiyun #define AFAB_EBI1_CH1_A_CLK 9 19*4882a593Smuzhiyun #define AFAB_AXI_S0_FCLK 10 20*4882a593Smuzhiyun #define AFAB_AXI_S1_FCLK 11 21*4882a593Smuzhiyun #define AFAB_AXI_S2_FCLK 12 22*4882a593Smuzhiyun #define AFAB_AXI_S3_FCLK 13 23*4882a593Smuzhiyun #define AFAB_AXI_S4_FCLK 14 24*4882a593Smuzhiyun #define SFAB_CORE_CLK 15 25*4882a593Smuzhiyun #define SFAB_AXI_S0_FCLK 16 26*4882a593Smuzhiyun #define SFAB_AXI_S1_FCLK 17 27*4882a593Smuzhiyun #define SFAB_AXI_S2_FCLK 18 28*4882a593Smuzhiyun #define SFAB_AXI_S3_FCLK 19 29*4882a593Smuzhiyun #define SFAB_AXI_S4_FCLK 20 30*4882a593Smuzhiyun #define SFAB_AHB_S0_FCLK 21 31*4882a593Smuzhiyun #define SFAB_AHB_S1_FCLK 22 32*4882a593Smuzhiyun #define SFAB_AHB_S2_FCLK 23 33*4882a593Smuzhiyun #define SFAB_AHB_S3_FCLK 24 34*4882a593Smuzhiyun #define SFAB_AHB_S4_FCLK 25 35*4882a593Smuzhiyun #define SFAB_AHB_S5_FCLK 26 36*4882a593Smuzhiyun #define SFAB_AHB_S6_FCLK 27 37*4882a593Smuzhiyun #define SFAB_AHB_S7_FCLK 28 38*4882a593Smuzhiyun #define QDSS_AT_CLK_SRC 29 39*4882a593Smuzhiyun #define QDSS_AT_CLK 30 40*4882a593Smuzhiyun #define QDSS_TRACECLKIN_CLK_SRC 31 41*4882a593Smuzhiyun #define QDSS_TRACECLKIN_CLK 32 42*4882a593Smuzhiyun #define QDSS_TSCTR_CLK_SRC 33 43*4882a593Smuzhiyun #define QDSS_TSCTR_CLK 34 44*4882a593Smuzhiyun #define SFAB_ADM0_M0_A_CLK 35 45*4882a593Smuzhiyun #define SFAB_ADM0_M1_A_CLK 36 46*4882a593Smuzhiyun #define SFAB_ADM0_M2_H_CLK 37 47*4882a593Smuzhiyun #define ADM0_CLK 38 48*4882a593Smuzhiyun #define ADM0_PBUS_CLK 39 49*4882a593Smuzhiyun #define MSS_XPU_CLK 40 50*4882a593Smuzhiyun #define IMEM0_A_CLK 41 51*4882a593Smuzhiyun #define QDSS_H_CLK 42 52*4882a593Smuzhiyun #define PCIE_A_CLK 43 53*4882a593Smuzhiyun #define PCIE_AUX_CLK 44 54*4882a593Smuzhiyun #define PCIE_PHY_REF_CLK 45 55*4882a593Smuzhiyun #define PCIE_H_CLK 46 56*4882a593Smuzhiyun #define SFAB_CLK_SRC 47 57*4882a593Smuzhiyun #define MAHB0_CLK 48 58*4882a593Smuzhiyun #define Q6SW_CLK_SRC 49 59*4882a593Smuzhiyun #define Q6SW_CLK 50 60*4882a593Smuzhiyun #define Q6FW_CLK_SRC 51 61*4882a593Smuzhiyun #define Q6FW_CLK 52 62*4882a593Smuzhiyun #define SFAB_MSS_M_A_CLK 53 63*4882a593Smuzhiyun #define SFAB_USB3_M_A_CLK 54 64*4882a593Smuzhiyun #define SFAB_LPASS_Q6_A_CLK 55 65*4882a593Smuzhiyun #define SFAB_AFAB_M_A_CLK 56 66*4882a593Smuzhiyun #define AFAB_SFAB_M0_A_CLK 57 67*4882a593Smuzhiyun #define AFAB_SFAB_M1_A_CLK 58 68*4882a593Smuzhiyun #define SFAB_SATA_S_H_CLK 59 69*4882a593Smuzhiyun #define DFAB_CLK_SRC 60 70*4882a593Smuzhiyun #define DFAB_CLK 61 71*4882a593Smuzhiyun #define SFAB_DFAB_M_A_CLK 62 72*4882a593Smuzhiyun #define DFAB_SFAB_M_A_CLK 63 73*4882a593Smuzhiyun #define DFAB_SWAY0_H_CLK 64 74*4882a593Smuzhiyun #define DFAB_SWAY1_H_CLK 65 75*4882a593Smuzhiyun #define DFAB_ARB0_H_CLK 66 76*4882a593Smuzhiyun #define DFAB_ARB1_H_CLK 67 77*4882a593Smuzhiyun #define PPSS_H_CLK 68 78*4882a593Smuzhiyun #define PPSS_PROC_CLK 69 79*4882a593Smuzhiyun #define PPSS_TIMER0_CLK 70 80*4882a593Smuzhiyun #define PPSS_TIMER1_CLK 71 81*4882a593Smuzhiyun #define PMEM_A_CLK 72 82*4882a593Smuzhiyun #define DMA_BAM_H_CLK 73 83*4882a593Smuzhiyun #define SIC_H_CLK 74 84*4882a593Smuzhiyun #define SPS_TIC_H_CLK 75 85*4882a593Smuzhiyun #define SLIMBUS_H_CLK 76 86*4882a593Smuzhiyun #define SLIMBUS_XO_SRC_CLK 77 87*4882a593Smuzhiyun #define CFPB_2X_CLK_SRC 78 88*4882a593Smuzhiyun #define CFPB_CLK 79 89*4882a593Smuzhiyun #define CFPB0_H_CLK 80 90*4882a593Smuzhiyun #define CFPB1_H_CLK 81 91*4882a593Smuzhiyun #define CFPB2_H_CLK 82 92*4882a593Smuzhiyun #define SFAB_CFPB_M_H_CLK 83 93*4882a593Smuzhiyun #define CFPB_MASTER_H_CLK 84 94*4882a593Smuzhiyun #define SFAB_CFPB_S_H_CLK 85 95*4882a593Smuzhiyun #define CFPB_SPLITTER_H_CLK 86 96*4882a593Smuzhiyun #define TSIF_H_CLK 87 97*4882a593Smuzhiyun #define TSIF_INACTIVITY_TIMERS_CLK 88 98*4882a593Smuzhiyun #define TSIF_REF_SRC 89 99*4882a593Smuzhiyun #define TSIF_REF_CLK 90 100*4882a593Smuzhiyun #define CE1_H_CLK 91 101*4882a593Smuzhiyun #define CE1_CORE_CLK 92 102*4882a593Smuzhiyun #define CE1_SLEEP_CLK 93 103*4882a593Smuzhiyun #define CE2_H_CLK 94 104*4882a593Smuzhiyun #define CE2_CORE_CLK 95 105*4882a593Smuzhiyun #define SFPB_H_CLK_SRC 97 106*4882a593Smuzhiyun #define SFPB_H_CLK 98 107*4882a593Smuzhiyun #define SFAB_SFPB_M_H_CLK 99 108*4882a593Smuzhiyun #define SFAB_SFPB_S_H_CLK 100 109*4882a593Smuzhiyun #define RPM_PROC_CLK 101 110*4882a593Smuzhiyun #define RPM_BUS_H_CLK 102 111*4882a593Smuzhiyun #define RPM_SLEEP_CLK 103 112*4882a593Smuzhiyun #define RPM_TIMER_CLK 104 113*4882a593Smuzhiyun #define RPM_MSG_RAM_H_CLK 105 114*4882a593Smuzhiyun #define PMIC_ARB0_H_CLK 106 115*4882a593Smuzhiyun #define PMIC_ARB1_H_CLK 107 116*4882a593Smuzhiyun #define PMIC_SSBI2_SRC 108 117*4882a593Smuzhiyun #define PMIC_SSBI2_CLK 109 118*4882a593Smuzhiyun #define SDC1_H_CLK 110 119*4882a593Smuzhiyun #define SDC2_H_CLK 111 120*4882a593Smuzhiyun #define SDC3_H_CLK 112 121*4882a593Smuzhiyun #define SDC4_H_CLK 113 122*4882a593Smuzhiyun #define SDC5_H_CLK 114 123*4882a593Smuzhiyun #define SDC1_SRC 115 124*4882a593Smuzhiyun #define SDC2_SRC 116 125*4882a593Smuzhiyun #define SDC3_SRC 117 126*4882a593Smuzhiyun #define SDC4_SRC 118 127*4882a593Smuzhiyun #define SDC5_SRC 119 128*4882a593Smuzhiyun #define SDC1_CLK 120 129*4882a593Smuzhiyun #define SDC2_CLK 121 130*4882a593Smuzhiyun #define SDC3_CLK 122 131*4882a593Smuzhiyun #define SDC4_CLK 123 132*4882a593Smuzhiyun #define SDC5_CLK 124 133*4882a593Smuzhiyun #define DFAB_A2_H_CLK 125 134*4882a593Smuzhiyun #define USB_HS1_H_CLK 126 135*4882a593Smuzhiyun #define USB_HS1_XCVR_SRC 127 136*4882a593Smuzhiyun #define USB_HS1_XCVR_CLK 128 137*4882a593Smuzhiyun #define USB_HSIC_H_CLK 129 138*4882a593Smuzhiyun #define USB_HSIC_XCVR_FS_SRC 130 139*4882a593Smuzhiyun #define USB_HSIC_XCVR_FS_CLK 131 140*4882a593Smuzhiyun #define USB_HSIC_SYSTEM_CLK_SRC 132 141*4882a593Smuzhiyun #define USB_HSIC_SYSTEM_CLK 133 142*4882a593Smuzhiyun #define CFPB0_C0_H_CLK 134 143*4882a593Smuzhiyun #define CFPB0_C1_H_CLK 135 144*4882a593Smuzhiyun #define CFPB0_D0_H_CLK 136 145*4882a593Smuzhiyun #define CFPB0_D1_H_CLK 137 146*4882a593Smuzhiyun #define USB_FS1_H_CLK 138 147*4882a593Smuzhiyun #define USB_FS1_XCVR_FS_SRC 139 148*4882a593Smuzhiyun #define USB_FS1_XCVR_FS_CLK 140 149*4882a593Smuzhiyun #define USB_FS1_SYSTEM_CLK 141 150*4882a593Smuzhiyun #define USB_FS2_H_CLK 142 151*4882a593Smuzhiyun #define USB_FS2_XCVR_FS_SRC 143 152*4882a593Smuzhiyun #define USB_FS2_XCVR_FS_CLK 144 153*4882a593Smuzhiyun #define USB_FS2_SYSTEM_CLK 145 154*4882a593Smuzhiyun #define GSBI_COMMON_SIM_SRC 146 155*4882a593Smuzhiyun #define GSBI1_H_CLK 147 156*4882a593Smuzhiyun #define GSBI2_H_CLK 148 157*4882a593Smuzhiyun #define GSBI3_H_CLK 149 158*4882a593Smuzhiyun #define GSBI4_H_CLK 150 159*4882a593Smuzhiyun #define GSBI5_H_CLK 151 160*4882a593Smuzhiyun #define GSBI6_H_CLK 152 161*4882a593Smuzhiyun #define GSBI7_H_CLK 153 162*4882a593Smuzhiyun #define GSBI8_H_CLK 154 163*4882a593Smuzhiyun #define GSBI9_H_CLK 155 164*4882a593Smuzhiyun #define GSBI10_H_CLK 156 165*4882a593Smuzhiyun #define GSBI11_H_CLK 157 166*4882a593Smuzhiyun #define GSBI12_H_CLK 158 167*4882a593Smuzhiyun #define GSBI1_UART_SRC 159 168*4882a593Smuzhiyun #define GSBI1_UART_CLK 160 169*4882a593Smuzhiyun #define GSBI2_UART_SRC 161 170*4882a593Smuzhiyun #define GSBI2_UART_CLK 162 171*4882a593Smuzhiyun #define GSBI3_UART_SRC 163 172*4882a593Smuzhiyun #define GSBI3_UART_CLK 164 173*4882a593Smuzhiyun #define GSBI4_UART_SRC 165 174*4882a593Smuzhiyun #define GSBI4_UART_CLK 166 175*4882a593Smuzhiyun #define GSBI5_UART_SRC 167 176*4882a593Smuzhiyun #define GSBI5_UART_CLK 168 177*4882a593Smuzhiyun #define GSBI6_UART_SRC 169 178*4882a593Smuzhiyun #define GSBI6_UART_CLK 170 179*4882a593Smuzhiyun #define GSBI7_UART_SRC 171 180*4882a593Smuzhiyun #define GSBI7_UART_CLK 172 181*4882a593Smuzhiyun #define GSBI8_UART_SRC 173 182*4882a593Smuzhiyun #define GSBI8_UART_CLK 174 183*4882a593Smuzhiyun #define GSBI9_UART_SRC 175 184*4882a593Smuzhiyun #define GSBI9_UART_CLK 176 185*4882a593Smuzhiyun #define GSBI10_UART_SRC 177 186*4882a593Smuzhiyun #define GSBI10_UART_CLK 178 187*4882a593Smuzhiyun #define GSBI11_UART_SRC 179 188*4882a593Smuzhiyun #define GSBI11_UART_CLK 180 189*4882a593Smuzhiyun #define GSBI12_UART_SRC 181 190*4882a593Smuzhiyun #define GSBI12_UART_CLK 182 191*4882a593Smuzhiyun #define GSBI1_QUP_SRC 183 192*4882a593Smuzhiyun #define GSBI1_QUP_CLK 184 193*4882a593Smuzhiyun #define GSBI2_QUP_SRC 185 194*4882a593Smuzhiyun #define GSBI2_QUP_CLK 186 195*4882a593Smuzhiyun #define GSBI3_QUP_SRC 187 196*4882a593Smuzhiyun #define GSBI3_QUP_CLK 188 197*4882a593Smuzhiyun #define GSBI4_QUP_SRC 189 198*4882a593Smuzhiyun #define GSBI4_QUP_CLK 190 199*4882a593Smuzhiyun #define GSBI5_QUP_SRC 191 200*4882a593Smuzhiyun #define GSBI5_QUP_CLK 192 201*4882a593Smuzhiyun #define GSBI6_QUP_SRC 193 202*4882a593Smuzhiyun #define GSBI6_QUP_CLK 194 203*4882a593Smuzhiyun #define GSBI7_QUP_SRC 195 204*4882a593Smuzhiyun #define GSBI7_QUP_CLK 196 205*4882a593Smuzhiyun #define GSBI8_QUP_SRC 197 206*4882a593Smuzhiyun #define GSBI8_QUP_CLK 198 207*4882a593Smuzhiyun #define GSBI9_QUP_SRC 199 208*4882a593Smuzhiyun #define GSBI9_QUP_CLK 200 209*4882a593Smuzhiyun #define GSBI10_QUP_SRC 201 210*4882a593Smuzhiyun #define GSBI10_QUP_CLK 202 211*4882a593Smuzhiyun #define GSBI11_QUP_SRC 203 212*4882a593Smuzhiyun #define GSBI11_QUP_CLK 204 213*4882a593Smuzhiyun #define GSBI12_QUP_SRC 205 214*4882a593Smuzhiyun #define GSBI12_QUP_CLK 206 215*4882a593Smuzhiyun #define GSBI1_SIM_CLK 207 216*4882a593Smuzhiyun #define GSBI2_SIM_CLK 208 217*4882a593Smuzhiyun #define GSBI3_SIM_CLK 209 218*4882a593Smuzhiyun #define GSBI4_SIM_CLK 210 219*4882a593Smuzhiyun #define GSBI5_SIM_CLK 211 220*4882a593Smuzhiyun #define GSBI6_SIM_CLK 212 221*4882a593Smuzhiyun #define GSBI7_SIM_CLK 213 222*4882a593Smuzhiyun #define GSBI8_SIM_CLK 214 223*4882a593Smuzhiyun #define GSBI9_SIM_CLK 215 224*4882a593Smuzhiyun #define GSBI10_SIM_CLK 216 225*4882a593Smuzhiyun #define GSBI11_SIM_CLK 217 226*4882a593Smuzhiyun #define GSBI12_SIM_CLK 218 227*4882a593Smuzhiyun #define USB_HSIC_HSIC_CLK_SRC 219 228*4882a593Smuzhiyun #define USB_HSIC_HSIC_CLK 220 229*4882a593Smuzhiyun #define USB_HSIC_HSIO_CAL_CLK 221 230*4882a593Smuzhiyun #define SPDM_CFG_H_CLK 222 231*4882a593Smuzhiyun #define SPDM_MSTR_H_CLK 223 232*4882a593Smuzhiyun #define SPDM_FF_CLK_SRC 224 233*4882a593Smuzhiyun #define SPDM_FF_CLK 225 234*4882a593Smuzhiyun #define SEC_CTRL_CLK 226 235*4882a593Smuzhiyun #define SEC_CTRL_ACC_CLK_SRC 227 236*4882a593Smuzhiyun #define SEC_CTRL_ACC_CLK 228 237*4882a593Smuzhiyun #define TLMM_H_CLK 229 238*4882a593Smuzhiyun #define TLMM_CLK 230 239*4882a593Smuzhiyun #define SFAB_MSS_S_H_CLK 231 240*4882a593Smuzhiyun #define MSS_SLP_CLK 232 241*4882a593Smuzhiyun #define MSS_Q6SW_JTAG_CLK 233 242*4882a593Smuzhiyun #define MSS_Q6FW_JTAG_CLK 234 243*4882a593Smuzhiyun #define MSS_S_H_CLK 235 244*4882a593Smuzhiyun #define MSS_CXO_SRC_CLK 236 245*4882a593Smuzhiyun #define SATA_H_CLK 237 246*4882a593Smuzhiyun #define SATA_CLK_SRC 238 247*4882a593Smuzhiyun #define SATA_RXOOB_CLK 239 248*4882a593Smuzhiyun #define SATA_PMALIVE_CLK 240 249*4882a593Smuzhiyun #define SATA_PHY_REF_CLK 241 250*4882a593Smuzhiyun #define TSSC_CLK_SRC 242 251*4882a593Smuzhiyun #define TSSC_CLK 243 252*4882a593Smuzhiyun #define PDM_SRC 244 253*4882a593Smuzhiyun #define PDM_CLK 245 254*4882a593Smuzhiyun #define GP0_SRC 246 255*4882a593Smuzhiyun #define GP0_CLK 247 256*4882a593Smuzhiyun #define GP1_SRC 248 257*4882a593Smuzhiyun #define GP1_CLK 249 258*4882a593Smuzhiyun #define GP2_SRC 250 259*4882a593Smuzhiyun #define GP2_CLK 251 260*4882a593Smuzhiyun #define MPM_CLK 252 261*4882a593Smuzhiyun #define EBI1_CLK_SRC 253 262*4882a593Smuzhiyun #define EBI1_CH0_CLK 254 263*4882a593Smuzhiyun #define EBI1_CH1_CLK 255 264*4882a593Smuzhiyun #define EBI1_2X_CLK 256 265*4882a593Smuzhiyun #define EBI1_CH0_DQ_CLK 257 266*4882a593Smuzhiyun #define EBI1_CH1_DQ_CLK 258 267*4882a593Smuzhiyun #define EBI1_CH0_CA_CLK 259 268*4882a593Smuzhiyun #define EBI1_CH1_CA_CLK 260 269*4882a593Smuzhiyun #define EBI1_XO_CLK 261 270*4882a593Smuzhiyun #define SFAB_SMPSS_S_H_CLK 262 271*4882a593Smuzhiyun #define PRNG_SRC 263 272*4882a593Smuzhiyun #define PRNG_CLK 264 273*4882a593Smuzhiyun #define PXO_SRC 265 274*4882a593Smuzhiyun #define LPASS_CXO_CLK 266 275*4882a593Smuzhiyun #define LPASS_PXO_CLK 267 276*4882a593Smuzhiyun #define SPDM_CY_PORT0_CLK 268 277*4882a593Smuzhiyun #define SPDM_CY_PORT1_CLK 269 278*4882a593Smuzhiyun #define SPDM_CY_PORT2_CLK 270 279*4882a593Smuzhiyun #define SPDM_CY_PORT3_CLK 271 280*4882a593Smuzhiyun #define SPDM_CY_PORT4_CLK 272 281*4882a593Smuzhiyun #define SPDM_CY_PORT5_CLK 273 282*4882a593Smuzhiyun #define SPDM_CY_PORT6_CLK 274 283*4882a593Smuzhiyun #define SPDM_CY_PORT7_CLK 275 284*4882a593Smuzhiyun #define PLL0 276 285*4882a593Smuzhiyun #define PLL0_VOTE 277 286*4882a593Smuzhiyun #define PLL3 278 287*4882a593Smuzhiyun #define PLL3_VOTE 279 288*4882a593Smuzhiyun #define PLL4_VOTE 280 289*4882a593Smuzhiyun #define PLL5 281 290*4882a593Smuzhiyun #define PLL5_VOTE 282 291*4882a593Smuzhiyun #define PLL6 283 292*4882a593Smuzhiyun #define PLL6_VOTE 284 293*4882a593Smuzhiyun #define PLL7_VOTE 285 294*4882a593Smuzhiyun #define PLL8 286 295*4882a593Smuzhiyun #define PLL8_VOTE 287 296*4882a593Smuzhiyun #define PLL9 288 297*4882a593Smuzhiyun #define PLL10 289 298*4882a593Smuzhiyun #define PLL11 290 299*4882a593Smuzhiyun #define PLL12 291 300*4882a593Smuzhiyun #define PLL13 292 301*4882a593Smuzhiyun #define PLL14 293 302*4882a593Smuzhiyun #define PLL14_VOTE 294 303*4882a593Smuzhiyun #define USB_HS3_H_CLK 295 304*4882a593Smuzhiyun #define USB_HS3_XCVR_SRC 296 305*4882a593Smuzhiyun #define USB_HS3_XCVR_CLK 297 306*4882a593Smuzhiyun #define USB_HS4_H_CLK 298 307*4882a593Smuzhiyun #define USB_HS4_XCVR_SRC 299 308*4882a593Smuzhiyun #define USB_HS4_XCVR_CLK 300 309*4882a593Smuzhiyun #define SATA_PHY_CFG_CLK 301 310*4882a593Smuzhiyun #define SATA_A_CLK 302 311*4882a593Smuzhiyun #define CE3_SRC 303 312*4882a593Smuzhiyun #define CE3_CORE_CLK 304 313*4882a593Smuzhiyun #define CE3_H_CLK 305 314*4882a593Smuzhiyun #define PLL16 306 315*4882a593Smuzhiyun #define PLL17 307 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun #endif 318