Searched refs:MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (Results 1 – 12 of 12) sorted by relevance
445 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in enable_lvds()501 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in enable_spi_display()533 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in enable_spi_display()
230 reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK; in setup_display()
162 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in setup_display()
1427 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK in select_ldb_di_clock_source()1435 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK in select_ldb_di_clock_source()
556 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in setup_display()
506 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in setup_display()
586 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in setup_display()
771 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in setup_display()
447 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) macro
708 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in setup_display()
642 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in setup_display()
446 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); in setup_display()