Searched refs:MAX_INTERFACE_NUM (Results 1 – 14 of 14) sorted by relevance
26 static struct write_supp_result wr_supp_res[MAX_INTERFACE_NUM][MAX_BUS_NUM];69 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_read_leveling()71 u32 data_read[MAX_INTERFACE_NUM + 1] = { 0 }; in ddr3_tip_dynamic_read_leveling()72 u8 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_read_leveling()97 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()134 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()153 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()157 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()216 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()293 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()[all …]
17 u32 nominal_adll[MAX_INTERFACE_NUM * MAX_BUS_NUM];18 enum hws_training_ip_stat train_status[MAX_INTERFACE_NUM];19 u8 result_mat[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];20 u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];22 u8 result_all_bit[MAX_BUS_NUM * BUS_WIDTH_IN_BITS * MAX_INTERFACE_NUM];23 u8 max_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];24 u8 min_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];25 u8 max_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];26 u8 min_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];27 u32 pbsdelay_per_pup[NUM_OF_PBS_MODES][MAX_INTERFACE_NUM][MAX_BUS_NUM];[all …]
17 #define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM)124 u32 reg_mr0[MAX_INTERFACE_NUM];125 u32 reg_mr1[MAX_INTERFACE_NUM];126 u32 reg_mr2[MAX_INTERFACE_NUM];127 u32 reg_m_r3[MAX_INTERFACE_NUM];135 u32 read_data_sample[MAX_INTERFACE_NUM];143 u32 read_data_ready[MAX_INTERFACE_NUM];
25 u8 current_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];26 u8 last_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];27 u16 current_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];28 u16 last_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];29 u8 lim_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];30 u8 interface_state[MAX_INTERFACE_NUM];31 u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];34 static u8 pup_st[MAX_BUS_NUM][MAX_INTERFACE_NUM];53 u32 data_read[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_write_additional_odt_setting()187 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()[all …]
101 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_reg_dump()107 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()121 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()352 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_log()490 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_print_stability_log()495 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()514 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()656 int read_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in read_adll_value()668 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in read_adll_value()690 int write_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in write_adll_value()[all …]
26 u32 start_if = 0, end_if = (MAX_INTERFACE_NUM - 1);27 u8 bus_end_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];28 u8 bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];29 u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];60 enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; in ddr3_tip_centralization()64 u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()68 u8 final_pup_window[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()77 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_centralization()84 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()107 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()[all …]
39 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_bist_activate()82 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_bist_activate()144 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_bist_read_result()193 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in hws_ddr3_run_bist()255 struct bist_result st_bist_result[MAX_INTERFACE_NUM]; in ddr3_tip_print_bist_res()259 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in ddr3_tip_print_bist_res()276 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in ddr3_tip_print_bist_res()
21 u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];23 u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *163 [MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search + in ddr3_tip_get_buf_ptr()191 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_ip_training()201 if (interface_num >= MAX_INTERFACE_NUM) { in ddr3_tip_ip_training()396 for (index_cnt = 0; index_cnt < MAX_INTERFACE_NUM; index_cnt++) { in ddr3_tip_ip_training()434 for (index_cnt = 0; index_cnt < MAX_INTERFACE_NUM; index_cnt++) { in ddr3_tip_ip_training()598 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_read_training_result()629 if (if_id >= MAX_INTERFACE_NUM) { in ddr3_tip_read_training_result()743 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()[all …]
201 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];249 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];264 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];269 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];284 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];336 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
49 enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];316 u32 data_read[MAX_INTERFACE_NUM]; in hws_ddr3_tip_init_controller()329 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()640 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()691 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_load_topology_map()937 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_if_polling()944 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_if_polling()989 u32 data_read[MAX_INTERFACE_NUM]; in ddr3_tip_bus_read()1071 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_bus_access()1092 u32 data_read[MAX_INTERFACE_NUM]; in is_bus_access_done()[all …]
340 int read_pup_value(int pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],342 int read_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],344 int write_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
10 #define MAX_INTERFACE_NUM 1 macro
113 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_static_round_trip_arr_build()376 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_static_alg()509 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_configure_phy()
103 struct if_params interface_params[MAX_INTERFACE_NUM];