1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Marvell International Ltd. and its affiliates 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DDR3_A38X_H 8*4882a593Smuzhiyun #define _DDR3_A38X_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MAX_INTERFACE_NUM 1 11*4882a593Smuzhiyun #define MAX_BUS_NUM 5 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "ddr3_hws_hw_training_def.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ECC_SUPPORT 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* right now, we're not supporting this in mainline */ 18*4882a593Smuzhiyun #undef SUPPORT_STATIC_DUNIT_CONFIG 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Controler bus divider 1 for 32 bit, 2 for 64 bit */ 21*4882a593Smuzhiyun #define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Tune internal training params values */ 24*4882a593Smuzhiyun #define TUNE_TRAINING_PARAMS_CK_DELAY 160 25*4882a593Smuzhiyun #define TUNE_TRAINING_PARAMS_CK_DELAY_16 160 26*4882a593Smuzhiyun #define TUNE_TRAINING_PARAMS_PFINGER 41 27*4882a593Smuzhiyun #define TUNE_TRAINING_PARAMS_NFINGER 43 28*4882a593Smuzhiyun #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xa 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define MARVELL_BOARD MARVELL_BOARD_ID_BASE 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define REG_DEVICE_SAR1_ADDR 0xe4204 34*4882a593Smuzhiyun #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17 35*4882a593Smuzhiyun #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* DRAM Windows */ 38*4882a593Smuzhiyun #define REG_XBAR_WIN_5_CTRL_ADDR 0x20050 39*4882a593Smuzhiyun #define REG_XBAR_WIN_5_BASE_ADDR 0x20054 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* DRAM Windows */ 42*4882a593Smuzhiyun #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 43*4882a593Smuzhiyun #define REG_XBAR_WIN_4_BASE_ADDR 0x20044 44*4882a593Smuzhiyun #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 45*4882a593Smuzhiyun #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 46*4882a593Smuzhiyun #define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0 47*4882a593Smuzhiyun #define REG_XBAR_WIN_16_BASE_ADDR 0x200d4 48*4882a593Smuzhiyun #define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc 49*4882a593Smuzhiyun #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win)) 52*4882a593Smuzhiyun #define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win)) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* SatR defined too change topology busWidth and ECC configuration */ 55*4882a593Smuzhiyun #define DDR_SATR_CONFIG_MASK_WIDTH 0x8 56*4882a593Smuzhiyun #define DDR_SATR_CONFIG_MASK_ECC 0x10 57*4882a593Smuzhiyun #define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define REG_SAMPLE_RESET_HIGH_ADDR 0x18600 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Matrix enables DRAM modes (bus width/ECC) per boardId */ 64*4882a593Smuzhiyun #define TOPOLOGY_UPDATE_32BIT 0 65*4882a593Smuzhiyun #define TOPOLOGY_UPDATE_32BIT_ECC 1 66*4882a593Smuzhiyun #define TOPOLOGY_UPDATE_16BIT 2 67*4882a593Smuzhiyun #define TOPOLOGY_UPDATE_16BIT_ECC 3 68*4882a593Smuzhiyun #define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4 69*4882a593Smuzhiyun #define TOPOLOGY_UPDATE { \ 70*4882a593Smuzhiyun /* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \ 71*4882a593Smuzhiyun {1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \ 72*4882a593Smuzhiyun {1, 1, 1, 1, 1}, /* DB_68XX_ID */ \ 73*4882a593Smuzhiyun {1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \ 74*4882a593Smuzhiyun {1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \ 75*4882a593Smuzhiyun {1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \ 76*4882a593Smuzhiyun {0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \ 77*4882a593Smuzhiyun {1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \ 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun enum { 81*4882a593Smuzhiyun CPU_1066MHZ_DDR_400MHZ, 82*4882a593Smuzhiyun CPU_RESERVED_DDR_RESERVED0, 83*4882a593Smuzhiyun CPU_667MHZ_DDR_667MHZ, 84*4882a593Smuzhiyun CPU_800MHZ_DDR_800MHZ, 85*4882a593Smuzhiyun CPU_RESERVED_DDR_RESERVED1, 86*4882a593Smuzhiyun CPU_RESERVED_DDR_RESERVED2, 87*4882a593Smuzhiyun CPU_RESERVED_DDR_RESERVED3, 88*4882a593Smuzhiyun LAST_FREQ 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define ACTIVE_INTERFACE_MASK 0x1 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* _DDR3_A38X_H */ 94