1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Marvell International Ltd. and its affiliates 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DDR_TOPOLOGY_DEF_H 8*4882a593Smuzhiyun #define _DDR_TOPOLOGY_DEF_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "ddr3_training_ip_def.h" 11*4882a593Smuzhiyun #include "ddr3_topology_def.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #if defined(CONFIG_ARMADA_38X) 14*4882a593Smuzhiyun #include "ddr3_a38x.h" 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* bus width in bits */ 18*4882a593Smuzhiyun enum hws_bus_width { 19*4882a593Smuzhiyun BUS_WIDTH_4, 20*4882a593Smuzhiyun BUS_WIDTH_8, 21*4882a593Smuzhiyun BUS_WIDTH_16, 22*4882a593Smuzhiyun BUS_WIDTH_32 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum hws_temperature { 26*4882a593Smuzhiyun HWS_TEMP_LOW, 27*4882a593Smuzhiyun HWS_TEMP_NORMAL, 28*4882a593Smuzhiyun HWS_TEMP_HIGH 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum hws_mem_size { 32*4882a593Smuzhiyun MEM_512M, 33*4882a593Smuzhiyun MEM_1G, 34*4882a593Smuzhiyun MEM_2G, 35*4882a593Smuzhiyun MEM_4G, 36*4882a593Smuzhiyun MEM_8G, 37*4882a593Smuzhiyun MEM_SIZE_LAST 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun enum hws_timing { 41*4882a593Smuzhiyun HWS_TIM_DEFAULT, 42*4882a593Smuzhiyun HWS_TIM_1T, 43*4882a593Smuzhiyun HWS_TIM_2T 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct bus_params { 47*4882a593Smuzhiyun /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ 48*4882a593Smuzhiyun u8 cs_bitmask; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * mirror enable/disable 52*4882a593Smuzhiyun * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...) 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun int mirror_enable_bitmask; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* DQS Swap (polarity) - true if enable */ 57*4882a593Smuzhiyun int is_dqs_swap; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* CK swap (polarity) - true if enable */ 60*4882a593Smuzhiyun int is_ck_swap; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct if_params { 64*4882a593Smuzhiyun /* bus configuration */ 65*4882a593Smuzhiyun struct bus_params as_bus_params[MAX_BUS_NUM]; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Speed Bin Table */ 68*4882a593Smuzhiyun enum hws_speed_bin speed_bin_index; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* bus width of memory */ 71*4882a593Smuzhiyun enum hws_bus_width bus_width; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Bus memory size (MBit) */ 74*4882a593Smuzhiyun enum hws_mem_size memory_size; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* The DDR frequency for each interfaces */ 77*4882a593Smuzhiyun enum hws_ddr_freq memory_freq; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* 80*4882a593Smuzhiyun * delay CAS Write Latency 81*4882a593Smuzhiyun * - 0 for using default value (jedec suggested) 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun u8 cas_wl; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * delay CAS Latency 87*4882a593Smuzhiyun * - 0 for using default value (jedec suggested) 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun u8 cas_l; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* operation temperature */ 92*4882a593Smuzhiyun enum hws_temperature interface_temp; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* 2T vs 1T mode (by default computed from number of CSs) */ 95*4882a593Smuzhiyun enum hws_timing timing; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct hws_topology_map { 99*4882a593Smuzhiyun /* Number of interfaces (default is 12) */ 100*4882a593Smuzhiyun u8 if_act_mask; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Controller configuration per interface */ 103*4882a593Smuzhiyun struct if_params interface_params[MAX_INTERFACE_NUM]; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* BUS per interface (default is 4) */ 106*4882a593Smuzhiyun u8 num_of_bus_per_interface; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* Bit mask for active buses */ 109*4882a593Smuzhiyun u8 bus_act_mask; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* DDR3 training global configuration parameters */ 113*4882a593Smuzhiyun struct tune_train_params { 114*4882a593Smuzhiyun u32 ck_delay; 115*4882a593Smuzhiyun u32 ck_delay_16; 116*4882a593Smuzhiyun u32 p_finger; 117*4882a593Smuzhiyun u32 n_finger; 118*4882a593Smuzhiyun u32 phy_reg3_val; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #endif /* _DDR_TOPOLOGY_DEF_H */ 122