Searched refs:IMX6UL_CLK_PLL4_AUDIO_DIV (Results 1 – 8 of 8) sorted by relevance
102 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;190 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
194 <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,197 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
132 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;258 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
101 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
63 #define IMX6UL_CLK_PLL4_AUDIO_DIV 50 macro
59 #define IMX6UL_CLK_PLL4_AUDIO_DIV 50 macro
102 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
219 hws[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", in imx6ul_clocks_init()