1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2016 PHYTEC Messtechnik GmbH 4*4882a593Smuzhiyun * Author: Christian Hemp <c.hemp@phytec.de> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite"; 9*4882a593Smuzhiyun compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun aliases { 12*4882a593Smuzhiyun rtc0 = &i2c_rtc; 13*4882a593Smuzhiyun rtc1 = &snvs_rtc; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun reg_sound_1v8: regulator-1v8 { 17*4882a593Smuzhiyun compatible = "regulator-fixed"; 18*4882a593Smuzhiyun regulator-name = "i2s-audio-1v8"; 19*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 20*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 21*4882a593Smuzhiyun status = "disabled"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg_sound_3v3: regulator-3v3 { 25*4882a593Smuzhiyun compatible = "regulator-fixed"; 26*4882a593Smuzhiyun regulator-name = "i2s-audio-3v3"; 27*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 28*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 29*4882a593Smuzhiyun status = "disabled"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reg_can1_en: regulator-can1 { 33*4882a593Smuzhiyun compatible = "regulator-fixed"; 34*4882a593Smuzhiyun pinctrl-names = "default"; 35*4882a593Smuzhiyun pinctrl-0 = <&princtrl_flexcan1_en>; 36*4882a593Smuzhiyun regulator-name = "Can"; 37*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 38*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 39*4882a593Smuzhiyun gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; 40*4882a593Smuzhiyun enable-active-high; 41*4882a593Smuzhiyun status = "disabled"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun reg_adc1_vref_3v3: regulator-vref-3v3 { 45*4882a593Smuzhiyun compatible = "regulator-fixed"; 46*4882a593Smuzhiyun regulator-name = "vref-3v3"; 47*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 48*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun sound: sound { 52*4882a593Smuzhiyun compatible = "simple-audio-card"; 53*4882a593Smuzhiyun simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; 54*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 55*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&dailink_master>; 56*4882a593Smuzhiyun simple-audio-card,frame-master = <&dailink_master>; 57*4882a593Smuzhiyun simple-audio-card,widgets = 58*4882a593Smuzhiyun "Line", "Line In", 59*4882a593Smuzhiyun "Line", "Line Out", 60*4882a593Smuzhiyun "Speaker", "Speaker"; 61*4882a593Smuzhiyun simple-audio-card,routing = 62*4882a593Smuzhiyun "Line Out", "LLOUT", 63*4882a593Smuzhiyun "Line Out", "RLOUT", 64*4882a593Smuzhiyun "Speaker", "SPOP", 65*4882a593Smuzhiyun "Speaker", "SPOM", 66*4882a593Smuzhiyun "LINE1L", "Line In", 67*4882a593Smuzhiyun "LINE1R", "Line In"; 68*4882a593Smuzhiyun status = "disabled"; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun simple-audio-card,cpu { 71*4882a593Smuzhiyun sound-dai = <&sai2>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun dailink_master: simple-audio-card,codec { 75*4882a593Smuzhiyun sound-dai = <&tlv320>; 76*4882a593Smuzhiyun clocks = <&clks IMX6UL_CLK_SAI2>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&adc1 { 83*4882a593Smuzhiyun pinctrl-names = "default"; 84*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_adc1>; 85*4882a593Smuzhiyun vref-supply = <®_adc1_vref_3v3>; 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * driver can not separate a specific channel so we request 4 channels 88*4882a593Smuzhiyun * here - we need only the fourth channel 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun num-channels = <4>; 91*4882a593Smuzhiyun status = "disabled"; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun&can1 { 95*4882a593Smuzhiyun pinctrl-names = "default"; 96*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexcan1>; 97*4882a593Smuzhiyun xceiver-supply = <®_can1_en>; 98*4882a593Smuzhiyun status = "disabled"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&clks { 102*4882a593Smuzhiyun assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 103*4882a593Smuzhiyun assigned-clock-rates = <786432000>; 104*4882a593Smuzhiyun}; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun&ecspi3 { 107*4882a593Smuzhiyun pinctrl-names = "default"; 108*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi3>; 109*4882a593Smuzhiyun cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; 110*4882a593Smuzhiyun status = "disabled"; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&fec2 { 114*4882a593Smuzhiyun pinctrl-names = "default"; 115*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet2>; 116*4882a593Smuzhiyun phy-mode = "rmii"; 117*4882a593Smuzhiyun phy-handle = <ðphy2>; 118*4882a593Smuzhiyun status = "disabled"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&i2c1 { 122*4882a593Smuzhiyun tlv320: codec@18 { 123*4882a593Smuzhiyun compatible = "ti,tlv320aic3007"; 124*4882a593Smuzhiyun #sound-dai-cells = <0>; 125*4882a593Smuzhiyun reg = <0x18>; 126*4882a593Smuzhiyun AVDD-supply = <®_sound_3v3>; 127*4882a593Smuzhiyun IOVDD-supply = <®_sound_3v3>; 128*4882a593Smuzhiyun DRVDD-supply = <®_sound_3v3>; 129*4882a593Smuzhiyun DVDD-supply = <®_sound_1v8>; 130*4882a593Smuzhiyun status = "disabled"; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun stmpe: touchscreen@44 { 134*4882a593Smuzhiyun compatible = "st,stmpe811"; 135*4882a593Smuzhiyun reg = <0x44>; 136*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 137*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 138*4882a593Smuzhiyun pinctrl-names = "default"; 139*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_stmpe>; 140*4882a593Smuzhiyun status = "disabled"; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun touchscreen { 143*4882a593Smuzhiyun compatible = "st,stmpe-ts"; 144*4882a593Smuzhiyun st,sample-time = <4>; 145*4882a593Smuzhiyun st,mod-12b = <1>; 146*4882a593Smuzhiyun st,ref-sel = <0>; 147*4882a593Smuzhiyun st,adc-freq = <1>; 148*4882a593Smuzhiyun st,ave-ctrl = <1>; 149*4882a593Smuzhiyun st,touch-det-delay = <2>; 150*4882a593Smuzhiyun st,settling = <2>; 151*4882a593Smuzhiyun st,fraction-z = <7>; 152*4882a593Smuzhiyun st,i-drive = <1>; 153*4882a593Smuzhiyun touchscreen-inverted-x = <1>; 154*4882a593Smuzhiyun touchscreen-inverted-y = <1>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun i2c_rtc: rtc@68 { 159*4882a593Smuzhiyun pinctrl-names = "default"; 160*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_rtc_int>; 161*4882a593Smuzhiyun compatible = "microcrystal,rv4162"; 162*4882a593Smuzhiyun reg = <0x68>; 163*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 164*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 165*4882a593Smuzhiyun status = "disabled"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun}; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun&mdio { 170*4882a593Smuzhiyun ethphy2: ethernet-phy@2 { 171*4882a593Smuzhiyun reg = <2>; 172*4882a593Smuzhiyun micrel,led-mode = <1>; 173*4882a593Smuzhiyun clocks = <&clks IMX6UL_CLK_ENET2_REF>; 174*4882a593Smuzhiyun clock-names = "rmii-ref"; 175*4882a593Smuzhiyun status = "disabled"; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun}; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun&pwm3 { 180*4882a593Smuzhiyun pinctrl-names = "default"; 181*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm3>; 182*4882a593Smuzhiyun status = "disabled"; 183*4882a593Smuzhiyun}; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun&sai2 { 186*4882a593Smuzhiyun pinctrl-names = "default"; 187*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sai2>; 188*4882a593Smuzhiyun assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 189*4882a593Smuzhiyun <&clks IMX6UL_CLK_SAI2>; 190*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 191*4882a593Smuzhiyun assigned-clock-rates = <0>, <19200000>; 192*4882a593Smuzhiyun fsl,sai-mclk-direction-output; 193*4882a593Smuzhiyun status = "disabled"; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&uart5 { 197*4882a593Smuzhiyun pinctrl-names = "default"; 198*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 199*4882a593Smuzhiyun uart-has-rtscts; 200*4882a593Smuzhiyun status = "disabled"; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&usbotg1 { 204*4882a593Smuzhiyun pinctrl-names = "default"; 205*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb_otg1_id>; 206*4882a593Smuzhiyun dr_mode = "otg"; 207*4882a593Smuzhiyun status = "disabled"; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&usbotg2 { 211*4882a593Smuzhiyun dr_mode = "host"; 212*4882a593Smuzhiyun disable-over-current; 213*4882a593Smuzhiyun status = "disabled"; 214*4882a593Smuzhiyun}; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun&usdhc1 { 217*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 218*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc1>; 219*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 220*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 221*4882a593Smuzhiyun cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 222*4882a593Smuzhiyun no-1-8-v; 223*4882a593Smuzhiyun keep-power-in-suspend; 224*4882a593Smuzhiyun wakeup-source; 225*4882a593Smuzhiyun status = "disabled"; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&iomuxc { 229*4882a593Smuzhiyun pinctrl_adc1: adc1grp { 230*4882a593Smuzhiyun fsl,pins = < 231*4882a593Smuzhiyun MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 232*4882a593Smuzhiyun >; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun pinctrl_ecspi3: ecspi3grp { 236*4882a593Smuzhiyun fsl,pins = < 237*4882a593Smuzhiyun MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 238*4882a593Smuzhiyun MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 239*4882a593Smuzhiyun MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 240*4882a593Smuzhiyun MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 241*4882a593Smuzhiyun >; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun pinctrl_enet2: enet2grp { 245*4882a593Smuzhiyun fsl,pins = < 246*4882a593Smuzhiyun MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 247*4882a593Smuzhiyun MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 248*4882a593Smuzhiyun MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 249*4882a593Smuzhiyun MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 250*4882a593Smuzhiyun MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 251*4882a593Smuzhiyun MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 252*4882a593Smuzhiyun MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 253*4882a593Smuzhiyun MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 254*4882a593Smuzhiyun >; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun pinctrl_flexcan1: flexcan1 { 258*4882a593Smuzhiyun fsl,pins = < 259*4882a593Smuzhiyun MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 260*4882a593Smuzhiyun MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 261*4882a593Smuzhiyun >; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun princtrl_flexcan1_en: flexcan1engrp { 265*4882a593Smuzhiyun fsl,pins = < 266*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 267*4882a593Smuzhiyun >; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun pinctrl_pwm3: pwm3grp { 271*4882a593Smuzhiyun fsl,pins = < 272*4882a593Smuzhiyun MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 273*4882a593Smuzhiyun >; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun pinctrl_rtc_int: rtcintgrp { 277*4882a593Smuzhiyun fsl,pins = < 278*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 279*4882a593Smuzhiyun >; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun pinctrl_sai2: sai2grp { 283*4882a593Smuzhiyun fsl,pins = < 284*4882a593Smuzhiyun MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 285*4882a593Smuzhiyun MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 286*4882a593Smuzhiyun MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 287*4882a593Smuzhiyun MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 288*4882a593Smuzhiyun MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 289*4882a593Smuzhiyun >; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun pinctrl_stmpe: stmpegrp { 293*4882a593Smuzhiyun fsl,pins = < 294*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 295*4882a593Smuzhiyun >; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 299*4882a593Smuzhiyun fsl,pins = < 300*4882a593Smuzhiyun MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 301*4882a593Smuzhiyun MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 302*4882a593Smuzhiyun MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 303*4882a593Smuzhiyun MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 304*4882a593Smuzhiyun >; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun pinctrl_usb_otg1_id: usbotg1idgrp { 308*4882a593Smuzhiyun fsl,pins = < 309*4882a593Smuzhiyun MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 310*4882a593Smuzhiyun >; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun pinctrl_usdhc1: usdhc1grp { 314*4882a593Smuzhiyun fsl,pins = < 315*4882a593Smuzhiyun MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 316*4882a593Smuzhiyun MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 317*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 318*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 319*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 320*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 321*4882a593Smuzhiyun MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 322*4882a593Smuzhiyun >; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 326*4882a593Smuzhiyun fsl,pins = < 327*4882a593Smuzhiyun MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 328*4882a593Smuzhiyun MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 329*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 330*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 331*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 332*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 333*4882a593Smuzhiyun >; 334*4882a593Smuzhiyun }; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 337*4882a593Smuzhiyun fsl,pins = < 338*4882a593Smuzhiyun MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 339*4882a593Smuzhiyun MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 340*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 341*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 342*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 343*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 344*4882a593Smuzhiyun >; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun}; 347