1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX6UL_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX6UL_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX6UL_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX6UL_CLK_CKIL 1 11*4882a593Smuzhiyun #define IMX6UL_CLK_CKIH 2 12*4882a593Smuzhiyun #define IMX6UL_CLK_OSC 3 13*4882a593Smuzhiyun #define IMX6UL_PLL1_BYPASS_SRC 4 14*4882a593Smuzhiyun #define IMX6UL_PLL2_BYPASS_SRC 5 15*4882a593Smuzhiyun #define IMX6UL_PLL3_BYPASS_SRC 6 16*4882a593Smuzhiyun #define IMX6UL_PLL4_BYPASS_SRC 7 17*4882a593Smuzhiyun #define IMX6UL_PLL5_BYPASS_SRC 8 18*4882a593Smuzhiyun #define IMX6UL_PLL6_BYPASS_SRC 9 19*4882a593Smuzhiyun #define IMX6UL_PLL7_BYPASS_SRC 10 20*4882a593Smuzhiyun #define IMX6UL_CLK_PLL1 11 21*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2 12 22*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3 13 23*4882a593Smuzhiyun #define IMX6UL_CLK_PLL4 14 24*4882a593Smuzhiyun #define IMX6UL_CLK_PLL5 15 25*4882a593Smuzhiyun #define IMX6UL_CLK_PLL6 16 26*4882a593Smuzhiyun #define IMX6UL_CLK_PLL7 17 27*4882a593Smuzhiyun #define IMX6UL_PLL1_BYPASS 18 28*4882a593Smuzhiyun #define IMX6UL_PLL2_BYPASS 19 29*4882a593Smuzhiyun #define IMX6UL_PLL3_BYPASS 20 30*4882a593Smuzhiyun #define IMX6UL_PLL4_BYPASS 21 31*4882a593Smuzhiyun #define IMX6UL_PLL5_BYPASS 22 32*4882a593Smuzhiyun #define IMX6UL_PLL6_BYPASS 23 33*4882a593Smuzhiyun #define IMX6UL_PLL7_BYPASS 24 34*4882a593Smuzhiyun #define IMX6UL_CLK_PLL1_SYS 25 35*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_BUS 26 36*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_USB_OTG 27 37*4882a593Smuzhiyun #define IMX6UL_CLK_PLL4_AUDIO 28 38*4882a593Smuzhiyun #define IMX6UL_CLK_PLL5_VIDEO 29 39*4882a593Smuzhiyun #define IMX6UL_CLK_PLL6_ENET 30 40*4882a593Smuzhiyun #define IMX6UL_CLK_PLL7_USB_HOST 31 41*4882a593Smuzhiyun #define IMX6UL_CLK_USBPHY1 32 42*4882a593Smuzhiyun #define IMX6UL_CLK_USBPHY2 33 43*4882a593Smuzhiyun #define IMX6UL_CLK_USBPHY1_GATE 34 44*4882a593Smuzhiyun #define IMX6UL_CLK_USBPHY2_GATE 35 45*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_PFD0 36 46*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_PFD1 37 47*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_PFD2 38 48*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_PFD3 39 49*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_PFD0 40 50*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_PFD1 41 51*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_PFD2 42 52*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_PFD3 43 53*4882a593Smuzhiyun #define IMX6UL_CLK_ENET_REF 44 54*4882a593Smuzhiyun #define IMX6UL_CLK_ENET2_REF 45 55*4882a593Smuzhiyun #define IMX6UL_CLK_ENET2_REF_125M 46 56*4882a593Smuzhiyun #define IMX6UL_CLK_ENET_PTP_REF 47 57*4882a593Smuzhiyun #define IMX6UL_CLK_ENET_PTP 48 58*4882a593Smuzhiyun #define IMX6UL_CLK_PLL4_POST_DIV 49 59*4882a593Smuzhiyun #define IMX6UL_CLK_PLL4_AUDIO_DIV 50 60*4882a593Smuzhiyun #define IMX6UL_CLK_PLL5_POST_DIV 51 61*4882a593Smuzhiyun #define IMX6UL_CLK_PLL5_VIDEO_DIV 52 62*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_198M 53 63*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_80M 54 64*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_60M 55 65*4882a593Smuzhiyun #define IMX6UL_CLK_STEP 56 66*4882a593Smuzhiyun #define IMX6UL_CLK_PLL1_SW 57 67*4882a593Smuzhiyun #define IMX6UL_CLK_AXI_ALT_SEL 58 68*4882a593Smuzhiyun #define IMX6UL_CLK_AXI_SEL 59 69*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH_PRE 60 70*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH2_PRE 61 71*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH_CLK2_SEL 62 72*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 73*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC1_SEL 64 74*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC2_SEL 65 75*4882a593Smuzhiyun #define IMX6UL_CLK_BCH_SEL 66 76*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_SEL 67 77*4882a593Smuzhiyun #define IMX6UL_CLK_EIM_SLOW_SEL 68 78*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF_SEL 69 79*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1_SEL 70 80*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2_SEL 71 81*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3_SEL 72 82*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_PRE_SEL 73 83*4882a593Smuzhiyun #define IMX6UL_CLK_SIM_PRE_SEL 74 84*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0_SEL 75 85*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI1_SEL 76 86*4882a593Smuzhiyun #define IMX6UL_CLK_ENFC_SEL 77 87*4882a593Smuzhiyun #define IMX6UL_CLK_CAN_SEL 78 88*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI_SEL 79 89*4882a593Smuzhiyun #define IMX6UL_CLK_UART_SEL 80 90*4882a593Smuzhiyun #define IMX6UL_CLK_QSPI1_SEL 81 91*4882a593Smuzhiyun #define IMX6UL_CLK_PERCLK_SEL 82 92*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_SEL 83 93*4882a593Smuzhiyun #define IMX6UL_CLK_SIM_SEL 84 94*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH 85 95*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH2 86 96*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 97*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0_DIV_7 88 98*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 99*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI1_DIV_7 90 100*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 101*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 102*4882a593Smuzhiyun #define IMX6UL_CLK_ARM 93 103*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH_CLK2 94 104*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH2_CLK2 95 105*4882a593Smuzhiyun #define IMX6UL_CLK_AHB 96 106*4882a593Smuzhiyun #define IMX6UL_CLK_MMDC_PODF 97 107*4882a593Smuzhiyun #define IMX6UL_CLK_AXI_PODF 98 108*4882a593Smuzhiyun #define IMX6UL_CLK_PERCLK 99 109*4882a593Smuzhiyun #define IMX6UL_CLK_IPG 100 110*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC1_PODF 101 111*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC2_PODF 102 112*4882a593Smuzhiyun #define IMX6UL_CLK_BCH_PODF 103 113*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_PODF 104 114*4882a593Smuzhiyun #define IMX6UL_CLK_EIM_SLOW_PODF 105 115*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF_PRED 106 116*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF_PODF 107 117*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1_PRED 108 118*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1_PODF 109 119*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2_PRED 110 120*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2_PODF 111 121*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3_PRED 112 122*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3_PODF 113 123*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_PRED 114 124*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_PODF 115 125*4882a593Smuzhiyun #define IMX6UL_CLK_SIM_PODF 116 126*4882a593Smuzhiyun #define IMX6UL_CLK_QSPI1_PDOF 117 127*4882a593Smuzhiyun #define IMX6UL_CLK_ENFC_PRED 118 128*4882a593Smuzhiyun #define IMX6UL_CLK_ENFC_PODF 119 129*4882a593Smuzhiyun #define IMX6UL_CLK_CAN_PODF 120 130*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI_PODF 121 131*4882a593Smuzhiyun #define IMX6UL_CLK_UART_PODF 122 132*4882a593Smuzhiyun #define IMX6UL_CLK_ADC1 123 133*4882a593Smuzhiyun #define IMX6UL_CLK_ADC2 124 134*4882a593Smuzhiyun #define IMX6UL_CLK_AIPSTZ1 125 135*4882a593Smuzhiyun #define IMX6UL_CLK_AIPSTZ2 126 136*4882a593Smuzhiyun #define IMX6UL_CLK_AIPSTZ3 127 137*4882a593Smuzhiyun #define IMX6UL_CLK_APBHDMA 128 138*4882a593Smuzhiyun #define IMX6UL_CLK_ASRC_IPG 129 139*4882a593Smuzhiyun #define IMX6UL_CLK_ASRC_MEM 130 140*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_BCH_APB 131 141*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_BCH 132 142*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_IO 133 143*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_APB 134 144*4882a593Smuzhiyun #define IMX6UL_CLK_CAAM_MEM 135 145*4882a593Smuzhiyun #define IMX6UL_CLK_CAAM_ACLK 136 146*4882a593Smuzhiyun #define IMX6UL_CLK_CAAM_IPG 137 147*4882a593Smuzhiyun #define IMX6UL_CLK_CSI 138 148*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI1 139 149*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI2 140 150*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI3 141 151*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI4 142 152*4882a593Smuzhiyun #define IMX6UL_CLK_EIM 143 153*4882a593Smuzhiyun #define IMX6UL_CLK_ENET 144 154*4882a593Smuzhiyun #define IMX6UL_CLK_ENET_AHB 145 155*4882a593Smuzhiyun #define IMX6UL_CLK_EPIT1 146 156*4882a593Smuzhiyun #define IMX6UL_CLK_EPIT2 147 157*4882a593Smuzhiyun #define IMX6UL_CLK_CAN1_IPG 148 158*4882a593Smuzhiyun #define IMX6UL_CLK_CAN1_SERIAL 149 159*4882a593Smuzhiyun #define IMX6UL_CLK_CAN2_IPG 150 160*4882a593Smuzhiyun #define IMX6UL_CLK_CAN2_SERIAL 151 161*4882a593Smuzhiyun #define IMX6UL_CLK_GPT1_BUS 152 162*4882a593Smuzhiyun #define IMX6UL_CLK_GPT1_SERIAL 153 163*4882a593Smuzhiyun #define IMX6UL_CLK_GPT2_BUS 154 164*4882a593Smuzhiyun #define IMX6UL_CLK_GPT2_SERIAL 155 165*4882a593Smuzhiyun #define IMX6UL_CLK_I2C1 156 166*4882a593Smuzhiyun #define IMX6UL_CLK_I2C2 157 167*4882a593Smuzhiyun #define IMX6UL_CLK_I2C3 158 168*4882a593Smuzhiyun #define IMX6UL_CLK_I2C4 159 169*4882a593Smuzhiyun #define IMX6UL_CLK_IOMUXC 160 170*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_APB 161 171*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_PIX 162 172*4882a593Smuzhiyun #define IMX6UL_CLK_MMDC_P0_FAST 163 173*4882a593Smuzhiyun #define IMX6UL_CLK_MMDC_P0_IPG 164 174*4882a593Smuzhiyun #define IMX6UL_CLK_OCOTP 165 175*4882a593Smuzhiyun #define IMX6UL_CLK_OCRAM 166 176*4882a593Smuzhiyun #define IMX6UL_CLK_PWM1 167 177*4882a593Smuzhiyun #define IMX6UL_CLK_PWM2 168 178*4882a593Smuzhiyun #define IMX6UL_CLK_PWM3 169 179*4882a593Smuzhiyun #define IMX6UL_CLK_PWM4 170 180*4882a593Smuzhiyun #define IMX6UL_CLK_PWM5 171 181*4882a593Smuzhiyun #define IMX6UL_CLK_PWM6 172 182*4882a593Smuzhiyun #define IMX6UL_CLK_PWM7 173 183*4882a593Smuzhiyun #define IMX6UL_CLK_PWM8 174 184*4882a593Smuzhiyun #define IMX6UL_CLK_PXP 175 185*4882a593Smuzhiyun #define IMX6UL_CLK_QSPI 176 186*4882a593Smuzhiyun #define IMX6UL_CLK_ROM 177 187*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1 178 188*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1_IPG 179 189*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2 180 190*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2_IPG 181 191*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3 182 192*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3_IPG 183 193*4882a593Smuzhiyun #define IMX6UL_CLK_SDMA 184 194*4882a593Smuzhiyun #define IMX6UL_CLK_SIM 185 195*4882a593Smuzhiyun #define IMX6UL_CLK_SIM_S 186 196*4882a593Smuzhiyun #define IMX6UL_CLK_SPBA 187 197*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF 188 198*4882a593Smuzhiyun #define IMX6UL_CLK_UART1_IPG 189 199*4882a593Smuzhiyun #define IMX6UL_CLK_UART1_SERIAL 190 200*4882a593Smuzhiyun #define IMX6UL_CLK_UART2_IPG 191 201*4882a593Smuzhiyun #define IMX6UL_CLK_UART2_SERIAL 192 202*4882a593Smuzhiyun #define IMX6UL_CLK_UART3_IPG 193 203*4882a593Smuzhiyun #define IMX6UL_CLK_UART3_SERIAL 194 204*4882a593Smuzhiyun #define IMX6UL_CLK_UART4_IPG 195 205*4882a593Smuzhiyun #define IMX6UL_CLK_UART4_SERIAL 196 206*4882a593Smuzhiyun #define IMX6UL_CLK_UART5_IPG 197 207*4882a593Smuzhiyun #define IMX6UL_CLK_UART5_SERIAL 198 208*4882a593Smuzhiyun #define IMX6UL_CLK_UART6_IPG 199 209*4882a593Smuzhiyun #define IMX6UL_CLK_UART6_SERIAL 200 210*4882a593Smuzhiyun #define IMX6UL_CLK_UART7_IPG 201 211*4882a593Smuzhiyun #define IMX6UL_CLK_UART7_SERIAL 202 212*4882a593Smuzhiyun #define IMX6UL_CLK_UART8_IPG 203 213*4882a593Smuzhiyun #define IMX6UL_CLK_UART8_SERIAL 204 214*4882a593Smuzhiyun #define IMX6UL_CLK_USBOH3 205 215*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC1 206 216*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC2 207 217*4882a593Smuzhiyun #define IMX6UL_CLK_WDOG1 208 218*4882a593Smuzhiyun #define IMX6UL_CLK_WDOG2 209 219*4882a593Smuzhiyun #define IMX6UL_CLK_WDOG3 210 220*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0 211 221*4882a593Smuzhiyun #define IMX6UL_CLK_AXI 212 222*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF_GCLK 213 223*4882a593Smuzhiyun #define IMX6UL_CLK_GPT_3M 214 224*4882a593Smuzhiyun #define IMX6UL_CLK_SIM2 215 225*4882a593Smuzhiyun #define IMX6UL_CLK_SIM1 216 226*4882a593Smuzhiyun #define IMX6UL_CLK_IPP_DI0 217 227*4882a593Smuzhiyun #define IMX6UL_CLK_IPP_DI1 218 228*4882a593Smuzhiyun #define IMX6UL_CA7_SECONDARY_SEL 219 229*4882a593Smuzhiyun #define IMX6UL_CLK_PER_BCH 220 230*4882a593Smuzhiyun #define IMX6UL_CLK_CSI_SEL 221 231*4882a593Smuzhiyun #define IMX6UL_CLK_CSI_PODF 222 232*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_120M 223 233*4882a593Smuzhiyun #define IMX6UL_CLK_KPP 224 234*4882a593Smuzhiyun #define IMX6ULL_CLK_ESAI_PRED 225 235*4882a593Smuzhiyun #define IMX6ULL_CLK_ESAI_PODF 226 236*4882a593Smuzhiyun #define IMX6ULL_CLK_ESAI_EXTAL 227 237*4882a593Smuzhiyun #define IMX6ULL_CLK_ESAI_MEM 228 238*4882a593Smuzhiyun #define IMX6ULL_CLK_ESAI_IPG 229 239*4882a593Smuzhiyun #define IMX6ULL_CLK_DCP_CLK 230 240*4882a593Smuzhiyun #define IMX6ULL_CLK_EPDC_PRE_SEL 231 241*4882a593Smuzhiyun #define IMX6ULL_CLK_EPDC_SEL 232 242*4882a593Smuzhiyun #define IMX6ULL_CLK_EPDC_PODF 233 243*4882a593Smuzhiyun #define IMX6ULL_CLK_EPDC_ACLK 234 244*4882a593Smuzhiyun #define IMX6ULL_CLK_EPDC_PIX 235 245*4882a593Smuzhiyun #define IMX6ULL_CLK_ESAI_SEL 236 246*4882a593Smuzhiyun #define IMX6UL_CLK_CKO1_SEL 237 247*4882a593Smuzhiyun #define IMX6UL_CLK_CKO1_PODF 238 248*4882a593Smuzhiyun #define IMX6UL_CLK_CKO1 239 249*4882a593Smuzhiyun #define IMX6UL_CLK_CKO2_SEL 240 250*4882a593Smuzhiyun #define IMX6UL_CLK_CKO2_PODF 241 251*4882a593Smuzhiyun #define IMX6UL_CLK_CKO2 242 252*4882a593Smuzhiyun #define IMX6UL_CLK_CKO 243 253*4882a593Smuzhiyun #define IMX6UL_CLK_GPIO1 244 254*4882a593Smuzhiyun #define IMX6UL_CLK_GPIO2 245 255*4882a593Smuzhiyun #define IMX6UL_CLK_GPIO3 246 256*4882a593Smuzhiyun #define IMX6UL_CLK_GPIO4 247 257*4882a593Smuzhiyun #define IMX6UL_CLK_GPIO5 248 258*4882a593Smuzhiyun #define IMX6UL_CLK_MMDC_P1_IPG 249 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun #define IMX6UL_CLK_END 250 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ 263