xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright (C) 2015 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/ {
6*4882a593Smuzhiyun	chosen {
7*4882a593Smuzhiyun		stdout-path = &uart1;
8*4882a593Smuzhiyun	};
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	memory@80000000 {
11*4882a593Smuzhiyun		device_type = "memory";
12*4882a593Smuzhiyun		reg = <0x80000000 0x20000000>;
13*4882a593Smuzhiyun	};
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	backlight_display: backlight-display {
16*4882a593Smuzhiyun		compatible = "pwm-backlight";
17*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
18*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
19*4882a593Smuzhiyun		default-brightness-level = <6>;
20*4882a593Smuzhiyun		status = "okay";
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	reg_sd1_vmmc: regulator-sd1-vmmc {
25*4882a593Smuzhiyun		compatible = "regulator-fixed";
26*4882a593Smuzhiyun		regulator-name = "VSD_3V3";
27*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
28*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
29*4882a593Smuzhiyun		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
30*4882a593Smuzhiyun		enable-active-high;
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	reg_peri_3v3: regulator-peri-3v3 {
34*4882a593Smuzhiyun		compatible = "regulator-fixed";
35*4882a593Smuzhiyun		pinctrl-names = "default";
36*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_peri_3v3>;
37*4882a593Smuzhiyun		regulator-name = "VPERI_3V3";
38*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
39*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
40*4882a593Smuzhiyun		gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
41*4882a593Smuzhiyun		/*
42*4882a593Smuzhiyun		 * If you want to want to make this dynamic please
43*4882a593Smuzhiyun		 * check schematics and test all affected peripherals:
44*4882a593Smuzhiyun		 *
45*4882a593Smuzhiyun		 * - sensors
46*4882a593Smuzhiyun		 * - ethernet phy
47*4882a593Smuzhiyun		 * - can
48*4882a593Smuzhiyun		 * - bluetooth
49*4882a593Smuzhiyun		 * - wm8960 audio codec
50*4882a593Smuzhiyun		 * - ov5640 camera
51*4882a593Smuzhiyun		 */
52*4882a593Smuzhiyun		regulator-always-on;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	reg_can_3v3: regulator-can-3v3 {
56*4882a593Smuzhiyun		compatible = "regulator-fixed";
57*4882a593Smuzhiyun		regulator-name = "can-3v3";
58*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
59*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
60*4882a593Smuzhiyun		gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	sound {
64*4882a593Smuzhiyun		compatible = "simple-audio-card";
65*4882a593Smuzhiyun		simple-audio-card,name = "mx6ul-wm8960";
66*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
67*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&dailink_master>;
68*4882a593Smuzhiyun		simple-audio-card,frame-master = <&dailink_master>;
69*4882a593Smuzhiyun		simple-audio-card,widgets =
70*4882a593Smuzhiyun			"Microphone", "Mic Jack",
71*4882a593Smuzhiyun			"Line", "Line In",
72*4882a593Smuzhiyun			"Line", "Line Out",
73*4882a593Smuzhiyun			"Speaker", "Speaker",
74*4882a593Smuzhiyun			"Headphone", "Headphone Jack";
75*4882a593Smuzhiyun		simple-audio-card,routing =
76*4882a593Smuzhiyun			"Headphone Jack", "HP_L",
77*4882a593Smuzhiyun			"Headphone Jack", "HP_R",
78*4882a593Smuzhiyun			"Speaker", "SPK_LP",
79*4882a593Smuzhiyun			"Speaker", "SPK_LN",
80*4882a593Smuzhiyun			"Speaker", "SPK_RP",
81*4882a593Smuzhiyun			"Speaker", "SPK_RN",
82*4882a593Smuzhiyun			"LINPUT1", "Mic Jack",
83*4882a593Smuzhiyun			"LINPUT3", "Mic Jack",
84*4882a593Smuzhiyun			"RINPUT1", "Mic Jack",
85*4882a593Smuzhiyun			"RINPUT2", "Mic Jack";
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		simple-audio-card,cpu {
88*4882a593Smuzhiyun			sound-dai = <&sai2>;
89*4882a593Smuzhiyun		};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun		dailink_master: simple-audio-card,codec {
92*4882a593Smuzhiyun			sound-dai = <&codec>;
93*4882a593Smuzhiyun			clocks = <&clks IMX6UL_CLK_SAI2>;
94*4882a593Smuzhiyun		};
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	spi4 {
98*4882a593Smuzhiyun		compatible = "spi-gpio";
99*4882a593Smuzhiyun		pinctrl-names = "default";
100*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_spi4>;
101*4882a593Smuzhiyun		status = "okay";
102*4882a593Smuzhiyun		gpio-sck = <&gpio5 11 0>;
103*4882a593Smuzhiyun		gpio-mosi = <&gpio5 10 0>;
104*4882a593Smuzhiyun		cs-gpios = <&gpio5 7 0>;
105*4882a593Smuzhiyun		num-chipselects = <1>;
106*4882a593Smuzhiyun		#address-cells = <1>;
107*4882a593Smuzhiyun		#size-cells = <0>;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun		gpio_spi: gpio@0 {
110*4882a593Smuzhiyun			compatible = "fairchild,74hc595";
111*4882a593Smuzhiyun			gpio-controller;
112*4882a593Smuzhiyun			#gpio-cells = <2>;
113*4882a593Smuzhiyun			reg = <0>;
114*4882a593Smuzhiyun			registers-number = <1>;
115*4882a593Smuzhiyun			spi-max-frequency = <100000>;
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	panel {
120*4882a593Smuzhiyun		compatible = "innolux,at043tn24";
121*4882a593Smuzhiyun		backlight = <&backlight_display>;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun		port {
124*4882a593Smuzhiyun			panel_in: endpoint {
125*4882a593Smuzhiyun				remote-endpoint = <&display_out>;
126*4882a593Smuzhiyun			};
127*4882a593Smuzhiyun		};
128*4882a593Smuzhiyun	};
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun&clks {
132*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
133*4882a593Smuzhiyun	assigned-clock-rates = <786432000>;
134*4882a593Smuzhiyun};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun&i2c2 {
137*4882a593Smuzhiyun	clock-frequency = <100000>;
138*4882a593Smuzhiyun	pinctrl-names = "default";
139*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
140*4882a593Smuzhiyun	status = "okay";
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	codec: wm8960@1a {
143*4882a593Smuzhiyun		#sound-dai-cells = <0>;
144*4882a593Smuzhiyun		compatible = "wlf,wm8960";
145*4882a593Smuzhiyun		reg = <0x1a>;
146*4882a593Smuzhiyun		wlf,shared-lrclk;
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&fec1 {
151*4882a593Smuzhiyun	pinctrl-names = "default";
152*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet1>;
153*4882a593Smuzhiyun	phy-mode = "rmii";
154*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
155*4882a593Smuzhiyun	phy-supply = <&reg_peri_3v3>;
156*4882a593Smuzhiyun	status = "okay";
157*4882a593Smuzhiyun};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun&fec2 {
160*4882a593Smuzhiyun	pinctrl-names = "default";
161*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet2>;
162*4882a593Smuzhiyun	phy-mode = "rmii";
163*4882a593Smuzhiyun	phy-handle = <&ethphy1>;
164*4882a593Smuzhiyun	phy-supply = <&reg_peri_3v3>;
165*4882a593Smuzhiyun	status = "okay";
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	mdio {
168*4882a593Smuzhiyun		#address-cells = <1>;
169*4882a593Smuzhiyun		#size-cells = <0>;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun		ethphy0: ethernet-phy@2 {
172*4882a593Smuzhiyun			reg = <2>;
173*4882a593Smuzhiyun			micrel,led-mode = <1>;
174*4882a593Smuzhiyun			clocks = <&clks IMX6UL_CLK_ENET_REF>;
175*4882a593Smuzhiyun			clock-names = "rmii-ref";
176*4882a593Smuzhiyun		};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun		ethphy1: ethernet-phy@1 {
179*4882a593Smuzhiyun			reg = <1>;
180*4882a593Smuzhiyun			micrel,led-mode = <1>;
181*4882a593Smuzhiyun			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
182*4882a593Smuzhiyun			clock-names = "rmii-ref";
183*4882a593Smuzhiyun		};
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun&can1 {
188*4882a593Smuzhiyun	pinctrl-names = "default";
189*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
190*4882a593Smuzhiyun	xceiver-supply = <&reg_can_3v3>;
191*4882a593Smuzhiyun	status = "okay";
192*4882a593Smuzhiyun};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun&can2 {
195*4882a593Smuzhiyun	pinctrl-names = "default";
196*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
197*4882a593Smuzhiyun	xceiver-supply = <&reg_can_3v3>;
198*4882a593Smuzhiyun	status = "okay";
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&i2c1 {
202*4882a593Smuzhiyun	clock-frequency = <100000>;
203*4882a593Smuzhiyun	pinctrl-names = "default";
204*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun	magnetometer@e {
208*4882a593Smuzhiyun		compatible = "fsl,mag3110";
209*4882a593Smuzhiyun		reg = <0x0e>;
210*4882a593Smuzhiyun		vdd-supply = <&reg_peri_3v3>;
211*4882a593Smuzhiyun		vddio-supply = <&reg_peri_3v3>;
212*4882a593Smuzhiyun	};
213*4882a593Smuzhiyun};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun&lcdif {
216*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
217*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
218*4882a593Smuzhiyun	pinctrl-names = "default";
219*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lcdif_dat
220*4882a593Smuzhiyun		     &pinctrl_lcdif_ctrl>;
221*4882a593Smuzhiyun	status = "okay";
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	port {
224*4882a593Smuzhiyun		display_out: endpoint {
225*4882a593Smuzhiyun			remote-endpoint = <&panel_in>;
226*4882a593Smuzhiyun		};
227*4882a593Smuzhiyun	};
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&pwm1 {
231*4882a593Smuzhiyun	#pwm-cells = <2>;
232*4882a593Smuzhiyun	pinctrl-names = "default";
233*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
234*4882a593Smuzhiyun	status = "okay";
235*4882a593Smuzhiyun};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun&qspi {
238*4882a593Smuzhiyun	pinctrl-names = "default";
239*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_qspi>;
240*4882a593Smuzhiyun	status = "okay";
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun	flash0: flash@0 {
243*4882a593Smuzhiyun		#address-cells = <1>;
244*4882a593Smuzhiyun		#size-cells = <1>;
245*4882a593Smuzhiyun		compatible = "micron,n25q256a", "jedec,spi-nor";
246*4882a593Smuzhiyun		spi-max-frequency = <29000000>;
247*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
248*4882a593Smuzhiyun		spi-tx-bus-width = <4>;
249*4882a593Smuzhiyun		reg = <0>;
250*4882a593Smuzhiyun	};
251*4882a593Smuzhiyun};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun&sai2 {
254*4882a593Smuzhiyun	pinctrl-names = "default";
255*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sai2>;
256*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
257*4882a593Smuzhiyun			  <&clks IMX6UL_CLK_SAI2>;
258*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
259*4882a593Smuzhiyun	assigned-clock-rates = <0>, <12288000>;
260*4882a593Smuzhiyun	fsl,sai-mclk-direction-output;
261*4882a593Smuzhiyun	status = "okay";
262*4882a593Smuzhiyun};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun&snvs_poweroff {
265*4882a593Smuzhiyun	status = "okay";
266*4882a593Smuzhiyun};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun&snvs_pwrkey {
269*4882a593Smuzhiyun	status = "okay";
270*4882a593Smuzhiyun};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun&tsc {
273*4882a593Smuzhiyun	pinctrl-names = "default";
274*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_tsc>;
275*4882a593Smuzhiyun	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
276*4882a593Smuzhiyun	measure-delay-time = <0xffff>;
277*4882a593Smuzhiyun	pre-charge-time = <0xfff>;
278*4882a593Smuzhiyun	status = "okay";
279*4882a593Smuzhiyun};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun&uart1 {
282*4882a593Smuzhiyun	pinctrl-names = "default";
283*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
284*4882a593Smuzhiyun	status = "okay";
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&uart2 {
288*4882a593Smuzhiyun	pinctrl-names = "default";
289*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
290*4882a593Smuzhiyun	uart-has-rtscts;
291*4882a593Smuzhiyun	status = "okay";
292*4882a593Smuzhiyun};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun&usbotg1 {
295*4882a593Smuzhiyun	dr_mode = "otg";
296*4882a593Smuzhiyun	pinctrl-names = "default";
297*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usb_otg1>;
298*4882a593Smuzhiyun	status = "okay";
299*4882a593Smuzhiyun};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun&usbotg2 {
302*4882a593Smuzhiyun	dr_mode = "host";
303*4882a593Smuzhiyun	disable-over-current;
304*4882a593Smuzhiyun	status = "okay";
305*4882a593Smuzhiyun};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun&usbphy1 {
308*4882a593Smuzhiyun	fsl,tx-d-cal = <106>;
309*4882a593Smuzhiyun};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun&usbphy2 {
312*4882a593Smuzhiyun	fsl,tx-d-cal = <106>;
313*4882a593Smuzhiyun};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun&usdhc1 {
316*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
317*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
318*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
319*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
320*4882a593Smuzhiyun	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
321*4882a593Smuzhiyun	keep-power-in-suspend;
322*4882a593Smuzhiyun	wakeup-source;
323*4882a593Smuzhiyun	vmmc-supply = <&reg_sd1_vmmc>;
324*4882a593Smuzhiyun	status = "okay";
325*4882a593Smuzhiyun};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun&usdhc2 {
328*4882a593Smuzhiyun	pinctrl-names = "default";
329*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
330*4882a593Smuzhiyun	no-1-8-v;
331*4882a593Smuzhiyun	broken-cd;
332*4882a593Smuzhiyun	keep-power-in-suspend;
333*4882a593Smuzhiyun	wakeup-source;
334*4882a593Smuzhiyun	status = "okay";
335*4882a593Smuzhiyun};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun&wdog1 {
338*4882a593Smuzhiyun	pinctrl-names = "default";
339*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_wdog>;
340*4882a593Smuzhiyun	fsl,ext-reset-output;
341*4882a593Smuzhiyun};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun&iomuxc {
344*4882a593Smuzhiyun	pinctrl-names = "default";
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun	pinctrl_csi1: csi1grp {
347*4882a593Smuzhiyun		fsl,pins = <
348*4882a593Smuzhiyun			MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b088
349*4882a593Smuzhiyun			MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b088
350*4882a593Smuzhiyun			MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b088
351*4882a593Smuzhiyun			MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b088
352*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b088
353*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b088
354*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b088
355*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b088
356*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b088
357*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b088
358*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b088
359*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b088
360*4882a593Smuzhiyun		>;
361*4882a593Smuzhiyun	};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun	pinctrl_enet1: enet1grp {
364*4882a593Smuzhiyun		fsl,pins = <
365*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
366*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
367*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
368*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
369*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
370*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
371*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
372*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
373*4882a593Smuzhiyun		>;
374*4882a593Smuzhiyun	};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun	pinctrl_enet2: enet2grp {
377*4882a593Smuzhiyun		fsl,pins = <
378*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
379*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
380*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
381*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
382*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
383*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
384*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
385*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
386*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
387*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
388*4882a593Smuzhiyun		>;
389*4882a593Smuzhiyun	};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1grp{
392*4882a593Smuzhiyun		fsl,pins = <
393*4882a593Smuzhiyun			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
394*4882a593Smuzhiyun			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
395*4882a593Smuzhiyun		>;
396*4882a593Smuzhiyun	};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2grp{
399*4882a593Smuzhiyun		fsl,pins = <
400*4882a593Smuzhiyun			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
401*4882a593Smuzhiyun			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
402*4882a593Smuzhiyun		>;
403*4882a593Smuzhiyun	};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
406*4882a593Smuzhiyun		fsl,pins = <
407*4882a593Smuzhiyun			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
408*4882a593Smuzhiyun			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
409*4882a593Smuzhiyun		>;
410*4882a593Smuzhiyun	};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
413*4882a593Smuzhiyun		fsl,pins = <
414*4882a593Smuzhiyun			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
415*4882a593Smuzhiyun			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
416*4882a593Smuzhiyun		>;
417*4882a593Smuzhiyun	};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun	pinctrl_lcdif_dat: lcdifdatgrp {
420*4882a593Smuzhiyun		fsl,pins = <
421*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
422*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
423*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
424*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
425*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
426*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
427*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
428*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
429*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
430*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
431*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
432*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
433*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
434*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
435*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
436*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
437*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
438*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
439*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
440*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
441*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
442*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
443*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
444*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
445*4882a593Smuzhiyun		>;
446*4882a593Smuzhiyun	};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun	pinctrl_lcdif_ctrl: lcdifctrlgrp {
449*4882a593Smuzhiyun		fsl,pins = <
450*4882a593Smuzhiyun			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
451*4882a593Smuzhiyun			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
452*4882a593Smuzhiyun			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
453*4882a593Smuzhiyun			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
454*4882a593Smuzhiyun			/* used for lcd reset */
455*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
456*4882a593Smuzhiyun		>;
457*4882a593Smuzhiyun	};
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun	pinctrl_qspi: qspigrp {
460*4882a593Smuzhiyun		fsl,pins = <
461*4882a593Smuzhiyun			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK	0x70a1
462*4882a593Smuzhiyun			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00	0x70a1
463*4882a593Smuzhiyun			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01	0x70a1
464*4882a593Smuzhiyun			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02	0x70a1
465*4882a593Smuzhiyun			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03	0x70a1
466*4882a593Smuzhiyun			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B	0x70a1
467*4882a593Smuzhiyun		>;
468*4882a593Smuzhiyun	};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun	pinctrl_sai2: sai2grp {
471*4882a593Smuzhiyun		fsl,pins = <
472*4882a593Smuzhiyun			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
473*4882a593Smuzhiyun			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
474*4882a593Smuzhiyun			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
475*4882a593Smuzhiyun			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
476*4882a593Smuzhiyun			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
477*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x17059
478*4882a593Smuzhiyun		>;
479*4882a593Smuzhiyun	};
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun	pinctrl_peri_3v3: peri3v3grp {
482*4882a593Smuzhiyun		fsl,pins = <
483*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0
484*4882a593Smuzhiyun		>;
485*4882a593Smuzhiyun	};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun	pinctrl_pwm1: pwm1grp {
488*4882a593Smuzhiyun		fsl,pins = <
489*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
490*4882a593Smuzhiyun		>;
491*4882a593Smuzhiyun	};
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun	pinctrl_sim2: sim2grp {
494*4882a593Smuzhiyun		fsl,pins = <
495*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD		0xb808
496*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK		0x31
497*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B		0xb808
498*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN		0xb808
499*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD		0xb809
500*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA02__GPIO4_IO23		0x3008
501*4882a593Smuzhiyun		>;
502*4882a593Smuzhiyun	};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun	pinctrl_spi4: spi4grp {
505*4882a593Smuzhiyun		fsl,pins = <
506*4882a593Smuzhiyun			MX6UL_PAD_BOOT_MODE0__GPIO5_IO10	0x70a1
507*4882a593Smuzhiyun			MX6UL_PAD_BOOT_MODE1__GPIO5_IO11	0x70a1
508*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x70a1
509*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x80000000
510*4882a593Smuzhiyun		>;
511*4882a593Smuzhiyun	};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun	pinctrl_tsc: tscgrp {
514*4882a593Smuzhiyun		fsl,pins = <
515*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01		0xb0
516*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02		0xb0
517*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03		0xb0
518*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04		0xb0
519*4882a593Smuzhiyun		>;
520*4882a593Smuzhiyun	};
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
523*4882a593Smuzhiyun		fsl,pins = <
524*4882a593Smuzhiyun			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
525*4882a593Smuzhiyun			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
526*4882a593Smuzhiyun		>;
527*4882a593Smuzhiyun	};
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
530*4882a593Smuzhiyun		fsl,pins = <
531*4882a593Smuzhiyun			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
532*4882a593Smuzhiyun			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
533*4882a593Smuzhiyun			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
534*4882a593Smuzhiyun			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
535*4882a593Smuzhiyun		>;
536*4882a593Smuzhiyun	};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun	pinctrl_usb_otg1: usbotg1grp {
539*4882a593Smuzhiyun		fsl,pins = <
540*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
541*4882a593Smuzhiyun		>;
542*4882a593Smuzhiyun	};
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
545*4882a593Smuzhiyun		fsl,pins = <
546*4882a593Smuzhiyun			MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
547*4882a593Smuzhiyun			MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
548*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
549*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
550*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
551*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
552*4882a593Smuzhiyun			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
553*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
554*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
555*4882a593Smuzhiyun		>;
556*4882a593Smuzhiyun	};
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
559*4882a593Smuzhiyun		fsl,pins = <
560*4882a593Smuzhiyun			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
561*4882a593Smuzhiyun			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
562*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
563*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
564*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
565*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun		>;
568*4882a593Smuzhiyun	};
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
571*4882a593Smuzhiyun		fsl,pins = <
572*4882a593Smuzhiyun			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
573*4882a593Smuzhiyun			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
574*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
575*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
576*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
577*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
578*4882a593Smuzhiyun		>;
579*4882a593Smuzhiyun	};
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
582*4882a593Smuzhiyun		fsl,pins = <
583*4882a593Smuzhiyun			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
584*4882a593Smuzhiyun			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
585*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
586*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
587*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
588*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
589*4882a593Smuzhiyun		>;
590*4882a593Smuzhiyun	};
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun	pinctrl_wdog: wdoggrp {
593*4882a593Smuzhiyun		fsl,pins = <
594*4882a593Smuzhiyun			MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
595*4882a593Smuzhiyun		>;
596*4882a593Smuzhiyun	};
597*4882a593Smuzhiyun};
598