xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6ul-pico.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2015 Technexion Ltd.
4*4882a593Smuzhiyun//
5*4882a593Smuzhiyun// Author: Wig Cheng  <wig.cheng@technexion.com>
6*4882a593Smuzhiyun//	   Richard Hu <richard.hu@technexion.com>
7*4882a593Smuzhiyun//	   Tapani Utriainen <tapani@technexion.com>
8*4882a593Smuzhiyun/dts-v1/;
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun#include "imx6ul.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	/* Will be filled by the bootloader */
14*4882a593Smuzhiyun	memory@80000000 {
15*4882a593Smuzhiyun		device_type = "memory";
16*4882a593Smuzhiyun		reg = <0x80000000 0>;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	chosen {
20*4882a593Smuzhiyun		stdout-path = &uart6;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	backlight: backlight {
24*4882a593Smuzhiyun		compatible = "pwm-backlight";
25*4882a593Smuzhiyun		pwms = <&pwm3 0 5000000>;
26*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
27*4882a593Smuzhiyun		default-brightness-level = <6>;
28*4882a593Smuzhiyun		status = "okay";
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	reg_2p5v: regulator-2p5v {
32*4882a593Smuzhiyun		compatible = "regulator-fixed";
33*4882a593Smuzhiyun		regulator-name = "2P5V";
34*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
35*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
36*4882a593Smuzhiyun	};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
39*4882a593Smuzhiyun		compatible = "regulator-fixed";
40*4882a593Smuzhiyun		regulator-name = "3P3V";
41*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
42*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	reg_sd1_vmmc: regulator-sd1-vmmc {
46*4882a593Smuzhiyun		compatible = "regulator-fixed";
47*4882a593Smuzhiyun		regulator-name = "VSD_3V3";
48*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
49*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
50*4882a593Smuzhiyun		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
51*4882a593Smuzhiyun		enable-active-high;
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-usb-otg-vbus {
55*4882a593Smuzhiyun		compatible = "regulator-fixed";
56*4882a593Smuzhiyun		pinctrl-names = "default";
57*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usb_otg1>;
58*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
59*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
60*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
61*4882a593Smuzhiyun		gpio = <&gpio1 6 0>;
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	reg_brcm: regulator-brcm {
65*4882a593Smuzhiyun		compatible = "regulator-fixed";
66*4882a593Smuzhiyun		enable-active-high;
67*4882a593Smuzhiyun		gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
68*4882a593Smuzhiyun		pinctrl-names = "default";
69*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_brcm_reg>;
70*4882a593Smuzhiyun		regulator-name = "brcm_reg";
71*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
72*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
73*4882a593Smuzhiyun		startup-delay-us = <200000>;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	panel {
77*4882a593Smuzhiyun		compatible = "vxt,vl050-8048nt-c01";
78*4882a593Smuzhiyun		backlight = <&backlight>;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun		port {
81*4882a593Smuzhiyun			panel_in: endpoint {
82*4882a593Smuzhiyun				remote-endpoint = <&display_out>;
83*4882a593Smuzhiyun			};
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&can1 {
89*4882a593Smuzhiyun	pinctrl-names = "default";
90*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
91*4882a593Smuzhiyun	status = "okay";
92*4882a593Smuzhiyun};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun&can2 {
95*4882a593Smuzhiyun	pinctrl-names = "default";
96*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
97*4882a593Smuzhiyun	status = "okay";
98*4882a593Smuzhiyun};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun&clks {
101*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
102*4882a593Smuzhiyun	assigned-clock-rates = <786432000>;
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&fec2 {
106*4882a593Smuzhiyun	pinctrl-names = "default";
107*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet2>;
108*4882a593Smuzhiyun	phy-mode = "rmii";
109*4882a593Smuzhiyun	phy-handle = <&ethphy1>;
110*4882a593Smuzhiyun	status = "okay";
111*4882a593Smuzhiyun	phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
112*4882a593Smuzhiyun	phy-reset-duration = <1>;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	mdio {
115*4882a593Smuzhiyun		#address-cells = <1>;
116*4882a593Smuzhiyun		#size-cells = <0>;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun		ethphy1: ethernet-phy@1 {
119*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c22";
120*4882a593Smuzhiyun			reg = <1>;
121*4882a593Smuzhiyun			max-speed = <100>;
122*4882a593Smuzhiyun			interrupt-parent = <&gpio5>;
123*4882a593Smuzhiyun			interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun	};
126*4882a593Smuzhiyun};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun&i2c1 {
129*4882a593Smuzhiyun	clock-frequency = <100000>;
130*4882a593Smuzhiyun	pinctrl-names = "default";
131*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
132*4882a593Smuzhiyun	status = "okay";
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	pmic: pfuze3000@8 {
135*4882a593Smuzhiyun		compatible = "fsl,pfuze3000";
136*4882a593Smuzhiyun		reg = <0x08>;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun		regulators {
139*4882a593Smuzhiyun			/* VDD_ARM_SOC_IN*/
140*4882a593Smuzhiyun			sw1b_reg: sw1b {
141*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
142*4882a593Smuzhiyun				regulator-max-microvolt = <1475000>;
143*4882a593Smuzhiyun				regulator-boot-on;
144*4882a593Smuzhiyun				regulator-always-on;
145*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
146*4882a593Smuzhiyun			};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun			/* DRAM */
149*4882a593Smuzhiyun			sw3a_reg: sw3 {
150*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
151*4882a593Smuzhiyun				regulator-max-microvolt = <1650000>;
152*4882a593Smuzhiyun				regulator-boot-on;
153*4882a593Smuzhiyun				regulator-always-on;
154*4882a593Smuzhiyun			};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun			/* DRAM */
157*4882a593Smuzhiyun			vref_reg: vrefddr {
158*4882a593Smuzhiyun				regulator-boot-on;
159*4882a593Smuzhiyun				regulator-always-on;
160*4882a593Smuzhiyun			};
161*4882a593Smuzhiyun		};
162*4882a593Smuzhiyun	};
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&lcdif {
166*4882a593Smuzhiyun	pinctrl-names = "default";
167*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
168*4882a593Smuzhiyun	status = "okay";
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun	port {
171*4882a593Smuzhiyun		display_out: endpoint {
172*4882a593Smuzhiyun			remote-endpoint = <&panel_in>;
173*4882a593Smuzhiyun		};
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun&pwm3 {
178*4882a593Smuzhiyun	#pwm-cells = <2>;
179*4882a593Smuzhiyun	pinctrl-names = "default";
180*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
181*4882a593Smuzhiyun	status = "okay";
182*4882a593Smuzhiyun};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun&pwm7 {
185*4882a593Smuzhiyun	pinctrl-names = "default";
186*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm7>;
187*4882a593Smuzhiyun	status = "okay";
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&pwm8 {
191*4882a593Smuzhiyun	pinctrl-names = "default";
192*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm8>;
193*4882a593Smuzhiyun	status = "okay";
194*4882a593Smuzhiyun};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun&sai1 {
197*4882a593Smuzhiyun	pinctrl-names = "default";
198*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sai1>;
199*4882a593Smuzhiyun	status = "okay";
200*4882a593Smuzhiyun};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun&uart3 {
203*4882a593Smuzhiyun	pinctrl-names = "default";
204*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
205*4882a593Smuzhiyun	uart-has-rtscts;
206*4882a593Smuzhiyun	status = "okay";
207*4882a593Smuzhiyun};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun&uart6 {
210*4882a593Smuzhiyun	pinctrl-names = "default";
211*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart6>;
212*4882a593Smuzhiyun	status = "okay";
213*4882a593Smuzhiyun};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun&usbotg1 {
216*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
217*4882a593Smuzhiyun	pinctrl-names = "default";
218*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usb_otg1_id>;
219*4882a593Smuzhiyun	dr_mode = "otg";
220*4882a593Smuzhiyun	disable-over-current;
221*4882a593Smuzhiyun	status = "okay";
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&usbotg2 {
225*4882a593Smuzhiyun	dr_mode = "host";
226*4882a593Smuzhiyun	disable-over-current;
227*4882a593Smuzhiyun	status = "okay";
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&usdhc1 {
231*4882a593Smuzhiyun	pinctrl-names = "default";
232*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
233*4882a593Smuzhiyun	bus-width = <8>;
234*4882a593Smuzhiyun	no-1-8-v;
235*4882a593Smuzhiyun	non-removable;
236*4882a593Smuzhiyun	keep-power-in-suspend;
237*4882a593Smuzhiyun	status = "okay";
238*4882a593Smuzhiyun};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun&usdhc2 {  /* Wifi SDIO */
241*4882a593Smuzhiyun	pinctrl-names = "default";
242*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
243*4882a593Smuzhiyun	no-1-8-v;
244*4882a593Smuzhiyun	non-removable;
245*4882a593Smuzhiyun	keep-power-in-suspend;
246*4882a593Smuzhiyun	wakeup-source;
247*4882a593Smuzhiyun	vmmc-supply = <&reg_brcm>;
248*4882a593Smuzhiyun	status = "okay";
249*4882a593Smuzhiyun};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun&wdog1 {
252*4882a593Smuzhiyun	pinctrl-names = "default";
253*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_wdog>;
254*4882a593Smuzhiyun	fsl,ext-reset-output;
255*4882a593Smuzhiyun};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun&iomuxc {
258*4882a593Smuzhiyun	pinctrl_brcm_reg: brcmreggrp {
259*4882a593Smuzhiyun		fsl,pins = <
260*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA06__GPIO4_IO08	0x10b0	/* WL_REG_ON */
261*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA04__GPIO4_IO06	0x10b0	/* WL_HOST_WAKE */
262*4882a593Smuzhiyun		>;
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	pinctrl_enet2: enet2grp {
266*4882a593Smuzhiyun		fsl,pins = <
267*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO	0x1b0b0
268*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_EN__ENET2_MDC	0x1b0b0
269*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
270*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
271*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
272*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
273*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
274*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
275*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
276*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
277*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x800
278*4882a593Smuzhiyun			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x79
279*4882a593Smuzhiyun		>;
280*4882a593Smuzhiyun	};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1grp {
283*4882a593Smuzhiyun		fsl,pins = <
284*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX	0x1b020
285*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX	0x1b020
286*4882a593Smuzhiyun		>;
287*4882a593Smuzhiyun	};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2grp {
290*4882a593Smuzhiyun		fsl,pins = <
291*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
292*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
293*4882a593Smuzhiyun		>;
294*4882a593Smuzhiyun	};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
297*4882a593Smuzhiyun		fsl,pins = <
298*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO02__I2C1_SCL		0x4001b8b0
299*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO03__I2C1_SDA		0x4001b8b0
300*4882a593Smuzhiyun		>;
301*4882a593Smuzhiyun	};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
304*4882a593Smuzhiyun		fsl,pins = <
305*4882a593Smuzhiyun			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
306*4882a593Smuzhiyun			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
307*4882a593Smuzhiyun		>;
308*4882a593Smuzhiyun	};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
311*4882a593Smuzhiyun		fsl,pins = <
312*4882a593Smuzhiyun			MX6UL_PAD_UART1_TX_DATA__I2C3_SCL	0x4001b8b0
313*4882a593Smuzhiyun			MX6UL_PAD_UART1_RX_DATA__I2C3_SDA	0x4001b8b0
314*4882a593Smuzhiyun			>;
315*4882a593Smuzhiyun	};
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun	pinctrl_lcdif_dat: lcdifdatgrp {
318*4882a593Smuzhiyun		fsl,pins = <
319*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x79
320*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x79
321*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x79
322*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x79
323*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x79
324*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x79
325*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x79
326*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x79
327*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x79
328*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x79
329*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x79
330*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x79
331*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x79
332*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x79
333*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x79
334*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x79
335*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x79
336*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x79
337*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x79
338*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x79
339*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x79
340*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x79
341*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x79
342*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x79
343*4882a593Smuzhiyun		>;
344*4882a593Smuzhiyun	};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun	pinctrl_lcdif_ctrl: lcdifctrlgrp {
347*4882a593Smuzhiyun		fsl,pins = <
348*4882a593Smuzhiyun			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x79
349*4882a593Smuzhiyun			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x79
350*4882a593Smuzhiyun			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x79
351*4882a593Smuzhiyun			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x79
352*4882a593Smuzhiyun			/* LCD reset */
353*4882a593Smuzhiyun			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x79
354*4882a593Smuzhiyun		>;
355*4882a593Smuzhiyun	};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun	pinctrl_pwm3: pwm3grp {
358*4882a593Smuzhiyun		fsl,pins = <
359*4882a593Smuzhiyun			MX6UL_PAD_NAND_ALE__PWM3_OUT		0x110b0
360*4882a593Smuzhiyun		>;
361*4882a593Smuzhiyun	};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun	pinctrl_pwm7: pwm7grp {
364*4882a593Smuzhiyun		fsl,pins = <
365*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT	0x110b0
366*4882a593Smuzhiyun		>;
367*4882a593Smuzhiyun	};
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun	pinctrl_pwm8: pwm8grp {
370*4882a593Smuzhiyun		fsl,pins = <
371*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_ER__PWM8_OUT		0x110b0
372*4882a593Smuzhiyun		>;
373*4882a593Smuzhiyun	};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun	pinctrl_sai1: sai1grp {
376*4882a593Smuzhiyun		fsl,pins = <
377*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC	0x1b0b0
378*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK	0x1b0b0
379*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA	0x110b0
380*4882a593Smuzhiyun			MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA	0x1f0b8
381*4882a593Smuzhiyun		>;
382*4882a593Smuzhiyun	};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
385*4882a593Smuzhiyun		fsl,pins = <
386*4882a593Smuzhiyun			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b0
387*4882a593Smuzhiyun			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b0
388*4882a593Smuzhiyun			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b0
389*4882a593Smuzhiyun			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b0b0
390*4882a593Smuzhiyun		>;
391*4882a593Smuzhiyun	};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun	pinctrl_uart5: uart5grp {
394*4882a593Smuzhiyun		fsl,pins = <
395*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX	0x1b0b1
396*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX	0x1b0b1
397*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
398*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
399*4882a593Smuzhiyun		>;
400*4882a593Smuzhiyun	};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun	pinctrl_uart6: uart6grp {
403*4882a593Smuzhiyun		fsl,pins = <
404*4882a593Smuzhiyun			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x1b0b1
405*4882a593Smuzhiyun			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x1b0b1
406*4882a593Smuzhiyun		>;
407*4882a593Smuzhiyun	};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun	pinctrl_usb_otg1: usbotg1grp {
410*4882a593Smuzhiyun		fsl,pins = <
411*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO06__GPIO1_IO06	0x10b0
412*4882a593Smuzhiyun			>;
413*4882a593Smuzhiyun	};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun	pinctrl_usb_otg1_id: usbotg1idgrp {
416*4882a593Smuzhiyun		fsl,pins = <
417*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
418*4882a593Smuzhiyun		>;
419*4882a593Smuzhiyun	};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
422*4882a593Smuzhiyun		fsl,pins = <
423*4882a593Smuzhiyun			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
424*4882a593Smuzhiyun			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10071
425*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
426*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
427*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
428*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
429*4882a593Smuzhiyun			MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B	0x03029
430*4882a593Smuzhiyun			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
431*4882a593Smuzhiyun			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
432*4882a593Smuzhiyun			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
433*4882a593Smuzhiyun			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
434*4882a593Smuzhiyun		>;
435*4882a593Smuzhiyun	};
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
438*4882a593Smuzhiyun		fsl,pins = <
439*4882a593Smuzhiyun			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
440*4882a593Smuzhiyun			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10059
441*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
442*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
443*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
444*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
445*4882a593Smuzhiyun		>;
446*4882a593Smuzhiyun	};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun	pinctrl_wdog: wdoggrp {
449*4882a593Smuzhiyun		fsl,pins = <
450*4882a593Smuzhiyun			MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
451*4882a593Smuzhiyun		>;
452*4882a593Smuzhiyun	};
453*4882a593Smuzhiyun};
454