1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX6UL_H 11*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX6UL_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define IMX6UL_CLK_DUMMY 0 14*4882a593Smuzhiyun #define IMX6UL_CLK_CKIL 1 15*4882a593Smuzhiyun #define IMX6UL_CLK_CKIH 2 16*4882a593Smuzhiyun #define IMX6UL_CLK_OSC 3 17*4882a593Smuzhiyun #define IMX6UL_PLL1_BYPASS_SRC 4 18*4882a593Smuzhiyun #define IMX6UL_PLL2_BYPASS_SRC 5 19*4882a593Smuzhiyun #define IMX6UL_PLL3_BYPASS_SRC 6 20*4882a593Smuzhiyun #define IMX6UL_PLL4_BYPASS_SRC 7 21*4882a593Smuzhiyun #define IMX6UL_PLL5_BYPASS_SRC 8 22*4882a593Smuzhiyun #define IMX6UL_PLL6_BYPASS_SRC 9 23*4882a593Smuzhiyun #define IMX6UL_PLL7_BYPASS_SRC 10 24*4882a593Smuzhiyun #define IMX6UL_CLK_PLL1 11 25*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2 12 26*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3 13 27*4882a593Smuzhiyun #define IMX6UL_CLK_PLL4 14 28*4882a593Smuzhiyun #define IMX6UL_CLK_PLL5 15 29*4882a593Smuzhiyun #define IMX6UL_CLK_PLL6 16 30*4882a593Smuzhiyun #define IMX6UL_CLK_PLL7 17 31*4882a593Smuzhiyun #define IMX6UL_PLL1_BYPASS 18 32*4882a593Smuzhiyun #define IMX6UL_PLL2_BYPASS 19 33*4882a593Smuzhiyun #define IMX6UL_PLL3_BYPASS 20 34*4882a593Smuzhiyun #define IMX6UL_PLL4_BYPASS 21 35*4882a593Smuzhiyun #define IMX6UL_PLL5_BYPASS 22 36*4882a593Smuzhiyun #define IMX6UL_PLL6_BYPASS 23 37*4882a593Smuzhiyun #define IMX6UL_PLL7_BYPASS 24 38*4882a593Smuzhiyun #define IMX6UL_CLK_PLL1_SYS 25 39*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_BUS 26 40*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_USB_OTG 27 41*4882a593Smuzhiyun #define IMX6UL_CLK_PLL4_AUDIO 28 42*4882a593Smuzhiyun #define IMX6UL_CLK_PLL5_VIDEO 29 43*4882a593Smuzhiyun #define IMX6UL_CLK_PLL6_ENET 30 44*4882a593Smuzhiyun #define IMX6UL_CLK_PLL7_USB_HOST 31 45*4882a593Smuzhiyun #define IMX6UL_CLK_USBPHY1 32 46*4882a593Smuzhiyun #define IMX6UL_CLK_USBPHY2 33 47*4882a593Smuzhiyun #define IMX6UL_CLK_USBPHY1_GATE 34 48*4882a593Smuzhiyun #define IMX6UL_CLK_USBPHY2_GATE 35 49*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_PFD0 36 50*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_PFD1 37 51*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_PFD2 38 52*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_PFD3 39 53*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_PFD0 40 54*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_PFD1 41 55*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_PFD2 42 56*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_PFD3 43 57*4882a593Smuzhiyun #define IMX6UL_CLK_ENET_REF 44 58*4882a593Smuzhiyun #define IMX6UL_CLK_ENET2_REF 45 59*4882a593Smuzhiyun #define IMX6UL_CLK_ENET2_REF_125M 46 60*4882a593Smuzhiyun #define IMX6UL_CLK_ENET_PTP_REF 47 61*4882a593Smuzhiyun #define IMX6UL_CLK_ENET_PTP 48 62*4882a593Smuzhiyun #define IMX6UL_CLK_PLL4_POST_DIV 49 63*4882a593Smuzhiyun #define IMX6UL_CLK_PLL4_AUDIO_DIV 50 64*4882a593Smuzhiyun #define IMX6UL_CLK_PLL5_POST_DIV 51 65*4882a593Smuzhiyun #define IMX6UL_CLK_PLL5_VIDEO_DIV 52 66*4882a593Smuzhiyun #define IMX6UL_CLK_PLL2_198M 53 67*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_80M 54 68*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_60M 55 69*4882a593Smuzhiyun #define IMX6UL_CLK_STEP 56 70*4882a593Smuzhiyun #define IMX6UL_CLK_PLL1_SW 57 71*4882a593Smuzhiyun #define IMX6UL_CLK_AXI_ALT_SEL 58 72*4882a593Smuzhiyun #define IMX6UL_CLK_AXI_SEL 59 73*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH_PRE 60 74*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH2_PRE 61 75*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH_CLK2_SEL 62 76*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 77*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC1_SEL 64 78*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC2_SEL 65 79*4882a593Smuzhiyun #define IMX6UL_CLK_BCH_SEL 66 80*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_SEL 67 81*4882a593Smuzhiyun #define IMX6UL_CLK_EIM_SLOW_SEL 68 82*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF_SEL 69 83*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1_SEL 70 84*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2_SEL 71 85*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3_SEL 72 86*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_PRE_SEL 73 87*4882a593Smuzhiyun #define IMX6UL_CLK_SIM_PRE_SEL 74 88*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0_SEL 75 89*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI1_SEL 76 90*4882a593Smuzhiyun #define IMX6UL_CLK_ENFC_SEL 77 91*4882a593Smuzhiyun #define IMX6UL_CLK_CAN_SEL 78 92*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI_SEL 79 93*4882a593Smuzhiyun #define IMX6UL_CLK_UART_SEL 80 94*4882a593Smuzhiyun #define IMX6UL_CLK_QSPI1_SEL 81 95*4882a593Smuzhiyun #define IMX6UL_CLK_PERCLK_SEL 82 96*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_SEL 83 97*4882a593Smuzhiyun #define IMX6UL_CLK_SIM_SEL 84 98*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH 85 99*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH2 86 100*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 101*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0_DIV_7 88 102*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 103*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI1_DIV_7 90 104*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 105*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 106*4882a593Smuzhiyun #define IMX6UL_CLK_ARM 93 107*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH_CLK2 94 108*4882a593Smuzhiyun #define IMX6UL_CLK_PERIPH2_CLK2 95 109*4882a593Smuzhiyun #define IMX6UL_CLK_AHB 96 110*4882a593Smuzhiyun #define IMX6UL_CLK_MMDC_PODF 97 111*4882a593Smuzhiyun #define IMX6UL_CLK_AXI_PODF 98 112*4882a593Smuzhiyun #define IMX6UL_CLK_PERCLK 99 113*4882a593Smuzhiyun #define IMX6UL_CLK_IPG 100 114*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC1_PODF 101 115*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC2_PODF 102 116*4882a593Smuzhiyun #define IMX6UL_CLK_BCH_PODF 103 117*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_PODF 104 118*4882a593Smuzhiyun #define IMX6UL_CLK_EIM_SLOW_PODF 105 119*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF_PRED 106 120*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF_PODF 107 121*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1_PRED 108 122*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1_PODF 109 123*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2_PRED 110 124*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2_PODF 111 125*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3_PRED 112 126*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3_PODF 113 127*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_PRED 114 128*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_PODF 115 129*4882a593Smuzhiyun #define IMX6UL_CLK_SIM_PODF 116 130*4882a593Smuzhiyun #define IMX6UL_CLK_QSPI1_PDOF 117 131*4882a593Smuzhiyun #define IMX6UL_CLK_ENFC_PRED 118 132*4882a593Smuzhiyun #define IMX6UL_CLK_ENFC_PODF 119 133*4882a593Smuzhiyun #define IMX6UL_CLK_CAN_PODF 120 134*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI_PODF 121 135*4882a593Smuzhiyun #define IMX6UL_CLK_UART_PODF 122 136*4882a593Smuzhiyun #define IMX6UL_CLK_ADC1 123 137*4882a593Smuzhiyun #define IMX6UL_CLK_ADC2 124 138*4882a593Smuzhiyun #define IMX6UL_CLK_AIPSTZ1 125 139*4882a593Smuzhiyun #define IMX6UL_CLK_AIPSTZ2 126 140*4882a593Smuzhiyun #define IMX6UL_CLK_AIPSTZ3 127 141*4882a593Smuzhiyun #define IMX6UL_CLK_APBHDMA 128 142*4882a593Smuzhiyun #define IMX6UL_CLK_ASRC_IPG 129 143*4882a593Smuzhiyun #define IMX6UL_CLK_ASRC_MEM 130 144*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_BCH_APB 131 145*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_BCH 132 146*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_IO 133 147*4882a593Smuzhiyun #define IMX6UL_CLK_GPMI_APB 134 148*4882a593Smuzhiyun #define IMX6UL_CLK_CAAM_MEM 135 149*4882a593Smuzhiyun #define IMX6UL_CLK_CAAM_ACLK 136 150*4882a593Smuzhiyun #define IMX6UL_CLK_CAAM_IPG 137 151*4882a593Smuzhiyun #define IMX6UL_CLK_CSI 138 152*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI1 139 153*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI2 140 154*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI3 141 155*4882a593Smuzhiyun #define IMX6UL_CLK_ECSPI4 142 156*4882a593Smuzhiyun #define IMX6UL_CLK_EIM 143 157*4882a593Smuzhiyun #define IMX6UL_CLK_ENET 144 158*4882a593Smuzhiyun #define IMX6UL_CLK_ENET_AHB 145 159*4882a593Smuzhiyun #define IMX6UL_CLK_EPIT1 146 160*4882a593Smuzhiyun #define IMX6UL_CLK_EPIT2 147 161*4882a593Smuzhiyun #define IMX6UL_CLK_CAN1_IPG 148 162*4882a593Smuzhiyun #define IMX6UL_CLK_CAN1_SERIAL 149 163*4882a593Smuzhiyun #define IMX6UL_CLK_CAN2_IPG 150 164*4882a593Smuzhiyun #define IMX6UL_CLK_CAN2_SERIAL 151 165*4882a593Smuzhiyun #define IMX6UL_CLK_GPT1_BUS 152 166*4882a593Smuzhiyun #define IMX6UL_CLK_GPT1_SERIAL 153 167*4882a593Smuzhiyun #define IMX6UL_CLK_GPT2_BUS 154 168*4882a593Smuzhiyun #define IMX6UL_CLK_GPT2_SERIAL 155 169*4882a593Smuzhiyun #define IMX6UL_CLK_I2C1 156 170*4882a593Smuzhiyun #define IMX6UL_CLK_I2C2 157 171*4882a593Smuzhiyun #define IMX6UL_CLK_I2C3 158 172*4882a593Smuzhiyun #define IMX6UL_CLK_I2C4 159 173*4882a593Smuzhiyun #define IMX6UL_CLK_IOMUXC 160 174*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_APB 161 175*4882a593Smuzhiyun #define IMX6UL_CLK_LCDIF_PIX 162 176*4882a593Smuzhiyun #define IMX6UL_CLK_MMDC_P0_FAST 163 177*4882a593Smuzhiyun #define IMX6UL_CLK_MMDC_P0_IPG 164 178*4882a593Smuzhiyun #define IMX6UL_CLK_OCOTP 165 179*4882a593Smuzhiyun #define IMX6UL_CLK_OCRAM 166 180*4882a593Smuzhiyun #define IMX6UL_CLK_PWM1 167 181*4882a593Smuzhiyun #define IMX6UL_CLK_PWM2 168 182*4882a593Smuzhiyun #define IMX6UL_CLK_PWM3 169 183*4882a593Smuzhiyun #define IMX6UL_CLK_PWM4 170 184*4882a593Smuzhiyun #define IMX6UL_CLK_PWM5 171 185*4882a593Smuzhiyun #define IMX6UL_CLK_PWM6 172 186*4882a593Smuzhiyun #define IMX6UL_CLK_PWM7 173 187*4882a593Smuzhiyun #define IMX6UL_CLK_PWM8 174 188*4882a593Smuzhiyun #define IMX6UL_CLK_PXP 175 189*4882a593Smuzhiyun #define IMX6UL_CLK_QSPI 176 190*4882a593Smuzhiyun #define IMX6UL_CLK_ROM 177 191*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1 178 192*4882a593Smuzhiyun #define IMX6UL_CLK_SAI1_IPG 179 193*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2 180 194*4882a593Smuzhiyun #define IMX6UL_CLK_SAI2_IPG 181 195*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3 182 196*4882a593Smuzhiyun #define IMX6UL_CLK_SAI3_IPG 183 197*4882a593Smuzhiyun #define IMX6UL_CLK_SDMA 184 198*4882a593Smuzhiyun #define IMX6UL_CLK_SIM 185 199*4882a593Smuzhiyun #define IMX6UL_CLK_SIM_S 186 200*4882a593Smuzhiyun #define IMX6UL_CLK_SPBA 187 201*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF 188 202*4882a593Smuzhiyun #define IMX6UL_CLK_UART1_IPG 189 203*4882a593Smuzhiyun #define IMX6UL_CLK_UART1_SERIAL 190 204*4882a593Smuzhiyun #define IMX6UL_CLK_UART2_IPG 191 205*4882a593Smuzhiyun #define IMX6UL_CLK_UART2_SERIAL 192 206*4882a593Smuzhiyun #define IMX6UL_CLK_UART3_IPG 193 207*4882a593Smuzhiyun #define IMX6UL_CLK_UART3_SERIAL 194 208*4882a593Smuzhiyun #define IMX6UL_CLK_UART4_IPG 195 209*4882a593Smuzhiyun #define IMX6UL_CLK_UART4_SERIAL 196 210*4882a593Smuzhiyun #define IMX6UL_CLK_UART5_IPG 197 211*4882a593Smuzhiyun #define IMX6UL_CLK_UART5_SERIAL 198 212*4882a593Smuzhiyun #define IMX6UL_CLK_UART6_IPG 199 213*4882a593Smuzhiyun #define IMX6UL_CLK_UART6_SERIAL 200 214*4882a593Smuzhiyun #define IMX6UL_CLK_UART7_IPG 201 215*4882a593Smuzhiyun #define IMX6UL_CLK_UART7_SERIAL 202 216*4882a593Smuzhiyun #define IMX6UL_CLK_UART8_IPG 203 217*4882a593Smuzhiyun #define IMX6UL_CLK_UART8_SERIAL 204 218*4882a593Smuzhiyun #define IMX6UL_CLK_USBOH3 205 219*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC1 206 220*4882a593Smuzhiyun #define IMX6UL_CLK_USDHC2 207 221*4882a593Smuzhiyun #define IMX6UL_CLK_WDOG1 208 222*4882a593Smuzhiyun #define IMX6UL_CLK_WDOG2 209 223*4882a593Smuzhiyun #define IMX6UL_CLK_WDOG3 210 224*4882a593Smuzhiyun #define IMX6UL_CLK_LDB_DI0 211 225*4882a593Smuzhiyun #define IMX6UL_CLK_AXI 212 226*4882a593Smuzhiyun #define IMX6UL_CLK_SPDIF_GCLK 213 227*4882a593Smuzhiyun #define IMX6UL_CLK_GPT_3M 214 228*4882a593Smuzhiyun #define IMX6UL_CLK_SIM2 215 229*4882a593Smuzhiyun #define IMX6UL_CLK_SIM1 216 230*4882a593Smuzhiyun #define IMX6UL_CLK_IPP_DI0 217 231*4882a593Smuzhiyun #define IMX6UL_CLK_IPP_DI1 218 232*4882a593Smuzhiyun #define IMX6UL_CA7_SECONDARY_SEL 219 233*4882a593Smuzhiyun #define IMX6UL_CLK_PER_BCH 220 234*4882a593Smuzhiyun #define IMX6UL_CLK_CSI_SEL 221 235*4882a593Smuzhiyun #define IMX6UL_CLK_CSI_PODF 222 236*4882a593Smuzhiyun #define IMX6UL_CLK_PLL3_120M 223 237*4882a593Smuzhiyun #define IMX6UL_CLK_KPP 224 238*4882a593Smuzhiyun /* For i.MX6ULL */ 239*4882a593Smuzhiyun #define IMX6UL_CLK_ESAI_SEL 224 240*4882a593Smuzhiyun #define IMX6UL_CLK_ESAI_PRED 225 241*4882a593Smuzhiyun #define IMX6UL_CLK_ESAI_PODF 226 242*4882a593Smuzhiyun #define IMX6UL_CLK_ESAI_EXTAL 227 243*4882a593Smuzhiyun #define IMX6UL_CLK_ESAI_MEM 228 244*4882a593Smuzhiyun #define IMX6UL_CLK_ESAI_IPG 229 245*4882a593Smuzhiyun #define IMX6UL_CLK_DCP_CLK 230 246*4882a593Smuzhiyun #define IMX6UL_CLK_EPDC_PRE_SEL 231 247*4882a593Smuzhiyun #define IMX6UL_CLK_EPDC_SEL 232 248*4882a593Smuzhiyun #define IMX6UL_CLK_EPDC_PODF 233 249*4882a593Smuzhiyun #define IMX6UL_CLK_EPDC_ACLK 234 250*4882a593Smuzhiyun #define IMX6UL_CLK_EPDC_PIX 235 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define IMX6UL_CLK_END 236 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ 255