Searched refs:FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT (Results 1 – 15 of 15) sorted by relevance
51 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in checkboard()103 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_mux_lane()
40 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
39 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
132 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in serdes_get_first_lane()355 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT, in fsl_serdes_init()
241 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in initialize_lane_to_slot()264 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
97 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_mux_lane_to_slot()
215 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_ft_fman_fixup_port()454 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in initialize_lane_to_slot()526 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
101 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in brd_mux_lane_to_slot()
50 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
166 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()
345 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in configure_vsc3316_3308()789 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in config_serdes1_refclks()
192 >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in initialize_lane_to_slot()
1764 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 macro1774 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 macro1780 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 macro1800 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 macro1814 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 macro
354 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in config_frontside_crossbar_vsc3316()
498 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in board_eth_init()